Semiconductor device including semiconductor memory circuit
View Patent ↗The semiconductor device including a memory circuit is configured to include a mode switching circuit additionally provided with a data comparison circuit which detects that a serial signal supplied to an input terminal for communication and a serial signal supplied to an input terminal used for a purpose other than communication are reversed from each other, a decoder circuit which detects that a serial signal carries predetermined data and which outputs a detection signal, a control signal generating circuit which generates a control signal, and a circuit which outputs a signal for switching to a test mode on the basis of the signals.
1. A semiconductor device including a semiconductor memory circuit, which has a clock input terminal to which a clock signal is supplied and a first input terminal for communication to which a data signal is supplied, and a mode switching circuit comprising:
a data comparison circuit which detects that data signals having phases that are reversed from each other have been supplied to the first input terminal and a second input terminal;
a first decoder circuit which detects that a first data signal of the data signals has been received and outputs a detection signal in combination with a detection signal of the data comparison circuit;
a second decoder circuit which detects that a second data signal of the data signals has been received and outputs a detection signal in combination with the detection signal of the data comparison circuit and the detection signal of the first decoder circuit; and
a circuit which outputs a switching signal for shifting to a test mode upon receipt of the detection signals from the first decoder circuit and the second decoder circuit.
2. The semiconductor device including a semiconductor memory circuit according to claim 1 , further comprising:
a control signal generating circuit which outputs a control signal,
wherein the detection signals of the first decoder circuit and the second decoder circuit and the switching signal are output upon receipt of the control signal.
3. The semiconductor device including a semiconductor memory circuit according to claim 2 , wherein the control signal generating circuit outputs the control signal according to the clock signal and a data signal at the first input terminal.
4. The semiconductor device including a semiconductor memory circuit according to claim 2 , wherein the control signal generating circuit outputs the control signal according to a signal at a chip select terminal.