IP Library Granted Patent US 8,786,101
Granted Patent B2
US 8,786,101 · App. 13/751,486 · Granted Jul 22, 2014

Contact structure in a memory device

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Quick Facts
Patent No.
US 8,786,101
App. No.
13/751,486
Granted
Jul 22, 2014
Kind
B2
Abstract

Annular, linear, and point contact structures are described which exhibit a greatly reduced susceptibility to process deviations caused by lithographic and deposition variations than does a conventional circular contact plug. In one embodiment, a standard conductive material such as carbon or titanium nitride is used to form the contact. In an alternative embodiment, a memory material itself is used to form the contact. These contact structures may be made by various processes, including chemical mechanical planarization and facet etching.

Claims (17)

1. A semiconductor device comprising:

a first conductive layer;

a first insulative layer disposed on the first conductive layer, wherein the first insulative layer comprises a contact opening formed through its entire thickness thereby terminating on the first conductive layer thereby providing a portion of the first conductive layer with no first insulative material thereover;

a second conductive layer disposed on the first insulative layer, the portion of the first conductive layer where the opening terminates and over which there is no first insulative layer, and in the contact opening the second conductive material comprising at least one of titanium nitride, titanium, aluminum, tungsten, tungsten silicide, and copper;

a second insulative layer disposed on the second conductive layer and in the contact opening, wherein portions of the second conductive layer are not covered by the second insulative layer; and

a conductive material disposed on the second insulative layer and in the contact opening, wherein the conductive material is in direct contact with the portions of the second conductive layer.

2. The semiconductor device of claim 1 , wherein the exposed portions of the second conductive layer form an annular contact.

3. The semiconductor device of claim 1 , wherein the first conductive layer comprises a lower electrode.

4. The semiconductors device of claim 1 , wherein the second conductive layer comprises an upper electrode.

5. A semiconductor device comprising:

a first conductive layer disposed on a substrate;

a first insulative layer disposed on the first conductive layer, wherein the first insulative layer has a contact opening formed through its entire thickness thereby exposing at least a portion of the first conductive layer;

a second conductive layer disposed on the first insulative layer on the exposed portion of the first conductive layer, and in the contact opening; and

a second insulative layer disposed on the second conductive layer and in the contact opening, wherein at least portions of the second conductive layer are not covered by the second insulative layer.

6. The semiconductor device of claim 5 , wherein the first conductive layer comprises a titanium nitride layer and a carbon layer deposited on the titanium nitride layer.

7. The semiconductor device of claim 5 , wherein the first insulative layer comprises boron and phosphorous doped silicon dioxide glass (BPSG).

8. The semiconductor device of claim 5 , wherein the contact opening comprises a depth and a diameter, and wherein the depth is greater than the diameter.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 18, 2013
From: MICRON TECHNOLOGY, INC.
To: ROUND ROCK RESEARCH, LLC
Reel/Frame 030864/0689 →