Hardware synthesis using thermally aware scheduling and binding
View Patent ↗Technologies are generally described for hardware synthesis using thermally aware scheduling and binding. Multiple versions of a hardware design may be generated, each having variations of schedule and binding results. The scheduling and binding may be performed such that thermal profiles of the multiple versions have thermal peaks that are distant between the versions. The increased physical distance between the thermal peaks of the versions can give the versions unique thermal characteristics. A schedule of rotation between the multiple versions of the design may be constructed such that the thermal profile of the integrated circuit balances out during operation. A linear programming framework may be used to analyze the multiple designs and construct a thermally aware rotation scheduling and binding. For example, the K most efficient versions may be selected and then durations for operating each version within a rotation may be determined.
1. An integrated circuit comprising:
a first version of a module to implement a function, wherein operation of the first version results in a first thermal energy pattern for the integrated circuit;
a second version of the module to implement the function, wherein operation of the second version results in a second thermal energy pattern for the integrated circuit;
wherein the first thermal energy pattern and the second thermal energy pattern are thermally diverse with respect to one another; and
a controller coupled to the first and second versions of the module and configured to implement a rotating schedule to select operation of the first version and the second version, wherein each of the first and second versions are operated for respective portions of the rotating schedule.
2. The integrated circuit of claim 1 wherein the controller is configured to implement the rotating schedule to reduce a peak operating temperature of the integrated circuit as compared to a peak operating temperature of another schedule of operation of the first and second version.
3. The integrated circuit of claim 1 wherein the controller is configured to implement the rotating schedule to reduce a peak thermal energy of the integrated circuit as compared to a peak thermal energy of another schedule of operation of the first and second version.
4. The integrated circuit of claim 1 wherein the controller is configured to implement the rotating schedule to reduce a peak power consumption of the integrated circuit as compared to a peak power consumption of another schedule of operation of the first and second version.
5. The integrated circuit of claim 1 wherein the first version is positioned away from the second version on the integrated circuit.
6. The integrated circuit of claim 1 wherein the first version has a first data path, the second version has a second data path, and the second data path differs from the first data path.
7. The integrated circuit of claim 1 wherein both the first version and the second version comprise adders and multipliers configured to perform the function.
8. The integrated circuit of claim 1 wherein the first version of the module is configured to implement a signal processing algorithm and the second version of the module separately is configured to implement the signal processing algorithm.
9. The integrated circuit of claim 1 wherein the controller is configured to select either the first version of the module or the second version of the module for operation only during a respective fractional duration of a rotation cycle.
10. The integrated circuit of claim 1 wherein the controller includes a finite state machine.
11. The integrated circuit of claim 1 wherein the respective portions of the operating schedule maintain a timing constraint associated with signal processing operations.
12. The integrated circuit of claim 1 , further comprising a third version of the module to implement the function, and wherein operation of the third version results in a third thermal energy pattern for the integrated circuit, and wherein the controller is configured to implement the rotating schedule for the first, second, and third versions, and each version is operated for respective portions of the rotating schedule.
13. The integrated circuit of claim 1 wherein the first version and the second version comprise a part of a number of versions of the module to implement the function, and wherein the number reduces a peak temperature associated with the integrated as compared to a peak operating temperature of an integrated circuit operating only a single version of the module.
14. The integrated circuit of claim 1 wherein the first version and the second version comprise a part of a number of versions of the module to implement the function, and wherein the number reduces a peak thermal energy of the integrated circuit as compared to a peak thermal energy of an integrated circuit operating only a single version of the module.
15. An integrated circuit, comprising:
a first version of a module which performs a function, wherein operation of the first version results in a first thermal energy pattern for the integrated circuit, the first version configured to operate for a first period of time; and
a second version of the module, the second circuit performing the function, wherein operation of the second version results in a second thermal energy pattern for the integrated circuit, the second version configured to operate for a second period of time, the second thermal energy pattern being thermally diverse with respect to the first thermal energy pattern; and
wherein the first version and the second version are configured to operate alternately to at least one of reduce a peak operating temperature of the integrated circuit, reduce a peak thermal energy of the integrated circuit, reduce a peak power consumption of the integrated circuit, or spread thermal energy generated by the modules across the integrated circuit.
16. The integrated circuit of claim 15 wherein the first version is positioned away from the module of the second version on the integrated circuit.
17. The integrated circuit of claim 15 wherein the first version has a first data path, the second version has a second data path, and the second data path differs from the first data path.
18. The integrated circuit of claim 15 wherein the first period of time and the second period of time maintain a timing constraint associated with signal processing operations.
19. The integrated circuit of claim 15 wherein both the first version and the second version comprise adders and multipliers configured to perform the function.
20. The integrated circuit of claim 15 wherein the first period of time for operation of the first version and the second period of time for operation of the second version operate to reduce a peak operating temperature of the integrated circuit.