Neuristor-based reservoir computing devices

1. A neuristor-based reservoir computing device comprising:

support circuitry formed in a complementary metal oxide semiconductor (CMOS) layer;

input nodes connected to the support circuitry;

output nodes connected to the support circuitry;

thin film neuristor nodes disposed over the CMOS layer, a first portion of the neuristor nodes connected to the input nodes and a second portion of the neuristor nodes connected to the output nodes; and

interconnections between the neuristor nodes to form a reservoir accepting input signals from the input nodes and outputting signals on the output nodes.

2. The computing device of claim 1 , in which the interconnections between the neuristor nodes are parametrically random.

3. The computing device of claim 1 , in which the interconnections between the neuristor nodes have parametrically random electrical resistances.

4. The computing device of claim 1 , in which the neuristor nodes comprise negative differential resistance elements.

5. The computing device of claim 4 , in which the neuristor nodes comprise current-controlled negative differential resistance materials.

6. The computing device of claim 1 , further comprising a memristor interposed between a neuristor node and an interconnection, the electrical resistance of the memristor determining a degree of activation/inhibition in a connection between the neuristor-based element and interconnection.

7. The computing device of claim 1 , in which neuristor nodes in the reservoir computer are divided into structured sub-domains, in which connections between the neuristor nodes in a sub-domain are parametrically random.

8. The computing device of claim 1 , in which the neuristor nodes each have the same design performance.

9. A neuristor-based reservoir computing device comprising:

support circuitry formed in a complementary metal oxide semiconductor (CMOS) layer;

input nodes connected to the support circuitry;

output nodes connected to the support circuitry;

thin film neuristor nodes disposed over the CMOS layer, a first portion of the neuristor nodes connected to the input nodes and a second portion of the neuristor nodes connected to the output nodes; and

interconnections between the neuristor nodes to form a reservoir accepting input signals from the input nodes and outputting signals on the output nodes;

in which the neuristor nodes each comprise a first channel comprising:

interconnect layer to receive an input signal;

an upper conductor to receive a biasing voltage;

a negative differential resistance (NDR) memristor; and

a capacitor, in which the memristor and the capacitor are sandwiched between the interconnect layer and upper conductor.

10. The computing device of claim 9 , in which the NDR memristor and capacitor are electrically parallel, in which charging of the capacitor induces delay in the NDR memristor switching behavior.

11. The computing device of claim 10 , in which an input signal from an input node is received by the interconnect layer, such that when a voltage difference between the input signal and a bias voltage applied to the upper conductor exceeds a threshold, the NDR memristor becomes conductive and generates an intermediate output signal.

12. The computing device of claim 11 , further comprising a second channel comprising:

a second interconnect layer;

a second upper conductor receiving a biasing voltage;

a second NDR memristor;

a capacitor, in which the second NDR memristor and the capacitor are sandwiched between the second interconnect layer and second upper conductor, in which the second interconnect layer receives the intermediate output signal.

13. The computing device of claim 9 , in which the neuristor nodes comprise Mott memristors.

14. A neuristor-based reservoir computing device comprising:

support circuitry formed in a complementary metal oxide semiconductor (CMOS) layer;

input vias passing upward from the support circuitry;

output vias passing upward from the support circuitry;

thin film neuristor nodes disposed over the CMOS layer, a first portion of the neuristor nodes connected to the input vias and a second portion of the neuristor nodes connected to the output vias, in which the neuristor nodes comprise:

interconnect layer receiving an input signal;

an upper conductor receiving a biasing voltage;

a negative differential resistance (NDR) memristor; and

a capacitor, in which the memristor and the capacitor are sandwiched between the interconnect layer and upper conductor; and

parametrically random interconnections between the neuristor nodes to form a reservoir accepting input signals from the input nodes and outputting signals on the output nodes.

15. A method for forming a neuristor-based reservoir computing device, the method comprising:

forming a structured silicon circuit with a number of connection points;

forming a thin film circuit over the structured silicon circuit by:

forming neuristor nodes; and

interconnecting the neuristor nodes, the interconnections comprising a plurality of feedback routes;

forming vias passing up from the connection points on the silicon circuit to electrically connect inputs from the silicon circuit to the thin film circuit; and

forming vias passing up from the connection points on the silicon circuit to electrically connect outputs from the thin film circuit to the structured silicon circuit.

16. The method of claim 15 , in which learning by the neuristor-based reservoir circuit comprises altering, with the structured silicon circuit, the inputs to the thin film circuit to achieve the desired output from the thin film circuit.

17. The method of claim 15 , further comprising designing parametrically random interconnections between the neuristor nodes within parametric parameters.

18. The method of claim 17 , in which the parametrically random interconnections between the neuristor nodes comprise random connections is at least one sub-domain of the thin film resistor.

19. The method of claim 17 , in which the neuristors are divided into sub-domains, in which interconnections with in the sub-domains are subject to different parametric parameters than interconnections between the sub-domains.

20. The method of claim 15 , in which interconnecting the neuristor nodes comprises building resistance elements with parametrically random electrical resistances into the interconnections.