LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices
View Patent ↗LDPC (Low Density Parity Check) codes with corresponding parity check matrices selectively constructed with CSI (Cyclic Shifted Identity) and null sub-matrices. An LDPC matrix corresponding to an LDPC code is employed within a communication device to encode and/or decode coded signals for use in any of a number of communication systems. The LDPC matrix is composed of a number of sub-matrices and may be partitioned into a left hand side matrix and a right hand side matrix. The right hand side matrix may include two sub-matrix diagonals therein that are composed entirely of CSI (Cyclic Shifted Identity) sub-matrices; one of these two sub-matrix diagonals is located on the center sub-matrix diagonal and the other is located just to the left thereof. All other sub-matrices of the right hand side matrix may be null sub-matrices (i.e., all elements therein are values of zero “0”).
1. An apparatus, comprising:
an input to receive a first LDPC (Low Density Parity Check) coded signal having a first code rate and a first block size and a second LDPC coded signal having a second code rate and a second block size; and
an LDPC decoder to decode the first LDPC coded signal using a first LDPC matrix, including a first plurality of sub-matrices, to make a first estimate of a first information bit and to decode the second LDPC coded signal using a second LDPC matrix, including a second plurality of sub-matrices, to make a second estimate of a second information bit; and wherein, within each of the first right hand side matrix and the second right hand side matrix:
each sub-matrix located on a respective diagonal is a respective CSI (Cyclic Shifted Identity) sub-matrix;
in every row between a top row and a next to bottom row, which is above and adjacent to a bottom row, inclusive, each sub-matrix located on a right hand side of the respective diagonal is a respective zero-valued sub-matrix;
the first code rate is one of 1/2, 2/3, 3/4, and 5/6; and
the second code rate is another one of 1/2, 2/3, 3/4, and 5/6 that is different from the first code rate.
2. The apparatus of claim 1 , wherein the input to receive a third LDPC coded signal having a third code rate and a fourth LDPC coded signal having a fourth code rate; and
the LDPC decoder to decode the third LDPC coded signal using a third LDPC matrix to make a third estimate of a third information bit and to decode the fourth LDPC coded signal using a fourth LDPC matrix to make a fourth estimate of a fourth information bit.
3. The apparatus of claim 1 , wherein each of the first plurality of sub-matrices having a first common size; and
each of the second plurality of sub-matrices having a second common size.
4. The apparatus of claim 1 , wherein each of the first plurality of sub-matrices and each of the second plurality of sub-matrices having a common size.
5. The apparatus of claim 1 , wherein the apparatus being a communication device operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.
6. An apparatus comprising:
an input to receive a first LDPC (Low Density Parity Check) coded signal having a first code rate and a second LDPC coded signal having a second code rate; and
an LDPC decoder to decode the first LDPC coded signal using a first LDPC matrix, including a first plurality of sub-matrices, to make a first estimate of a first information bit and to decode the second LDPC coded signal using a second LDPC matrix, including a second plurality of sub-matrices, to make a second estimate of a second information bit; and wherein, within each of the first right hand side matrix and the second right hand side matrix:
each sub-matrix located on a respective diagonal is a respective CSI (Cyclic Shifted Identity) sub-matrix; and
in every row between a top row and a next to bottom, which is above and adjacent to a bottom row, inclusive, each sub-matrix located on a right hand side of the respective diagonal is a respective zero-valued sub-matrix.
7. The apparatus of claim 6 , wherein the first code rate is one of 1/2, 2/3, 3/4, and 5/6; and
the second code rate is another one of 1/2, 2/3, 3/4, and 5/6 that is different from the first code rate.
8. The apparatus of claim 6 , wherein the first LDPC coded signal having a first block size and the second LDPC coded signal having a second block size.
9. The apparatus of claim 6 , wherein the input to receive a third LDPC coded signal having a third code rate and a fourth LDPC coded signal having a fourth code rate;
the LDPC decoder to decode the third LDPC coded signal using a third LDPC matrix to make a third estimate of a third information bit and to decode the fourth LDPC coded signal using a fourth LDPC matrix to make a fourth estimate of a fourth information bit;
the first code rate is 1/2;
the second code rate is 2/3;
the third code rate is 3/4; and
the fourth code rate is 5/6.
10. The apparatus of claim 9 , wherein the first LDPC coded signal having a first block size;
the second LDPC coded signal having a second block size;
the third LDPC coded signal having a third block size; and
the fourth LDPC coded signal having a fourth block size.
11. The apparatus of claim 6 , wherein each of the first plurality of sub-matrices having a first common size; and
each of the second plurality of sub-matrices having a second common size.
12. The apparatus of claim 6 , wherein each of the first plurality of sub-matrices and each of the second plurality of sub-matrices having a common size.
13. The apparatus of claim 6 , wherein the apparatus being a communication device operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.
14. A method for execution by a communication device, the method comprising:
via an input of the communication device, receiving a first LDPC (Low Density Parity Check) coded signal having a first code rate and a second LDPC coded signal having a second code rate;
decoding the first LDPC coded signal using a first LDPC matrix, including a first plurality of sub-matrices, to make a first estimate of a first information bit; and
decoding the second LDPC coded signal using a second LDPC matrix, including a second plurality of sub-matrices, to make a second estimate of a second information bit; and wherein, within each of the first right hand side matrix and the second right hand side matrix:
each sub-matrix located on a respective diagonal is a respective CSI (Cyclic Shifted Identity) sub-matrix; and
in every row between a top row and a next to bottom row, which is above and adjacent to a bottom row, inclusive, each sub-matrix located on a right hand side of the respective diagonal is a respective zero-valued sub-matrix.
15. The method of claim 14 , wherein the first code rate is one of 1/2, 2/3, 3/4, and 5/6; and
the second code rate is another one of 1/2, 2/3, 3/4, and 5/6 that is different from the first code rate.
16. The method of claim 14 , wherein the first LDPC coded signal having a first block size and the second LDPC coded signal having a second block size.
17. The method of claim 14 , further comprising:
via the input of the communication device, receiving a third LDPC coded signal having a third code rate and a fourth LDPC coded signal having a fourth code rate;
decoding the third LDPC coded signal using a third LDPC matrix to make a third estimate of a third information bit; and
decoding the fourth LDPC coded signal using a fourth LDPC matrix to make a fourth estimate of a fourth information bit; and wherein:
the first code rate is 1/2;
the second code rate is 2/3;
the third code rate is 3/4; and
the fourth code rate is 5/6.
18. The method of claim 17 , wherein the first LDPC coded signal having a first block size;
the second LDPC coded signal having a second block size;
the third LDPC coded signal having a third block size; and
the fourth LDPC coded signal having a fourth block size.
19. The method of claim 14 , wherein each of the first plurality of sub-matrices having a first common size; and
each of the second plurality of sub-matrices having a second common size.
20. The method of claim 14 , wherein the communication device operative within at least one of a satellite communication system, a wireless communication system, a wired communication system, and a fiber-optic communication system.