Receiver architecture and methods for demodulating quadrature phase shift keying signals

1. A receiver comprising:

a filter configured to receive a quadrature phase shift keying (“QPSK”) signal;

an amplifier coupled with said filter; and

a QPSK decomposition filter coupled with said amplifier, said QPSK decomposition filter configured to:

generate a first binary phase shift keying (“BPSK”) modulated signal based on said QPSK signal and a second BPSK modulated signal based on said QPSK signal, and

select between a first phase-shifted signal and a second phase-shifted signal, based on a phase of a product of said first phase-shifted signal and said second phase-shifted signal, to generate said first BPSK signal and said second BPSK signal.

2. A receiver comprising:

a filter configured to receive a quadrature phase shift keying (“QPSK”) signal;

an amplifier coupled with said filter; and

a QPSK decomposition filter coupled with said amplifier,

said QPSK decomposition filter including:

a first phase shifter configured to generate a first phase-shifted signal with a phase shifted by a positive forty-five degrees from a phase of said QPSK signal, and

a second phase shifter configured to generate a second phase-shifted signal with a phase shifted by a negative forty-five degrees from said phase of said QPSK signal,

said QPSK decomposition filter configured to:

generate a first binary phase shift keying (“BPSK”) modulated signal based on said QPSK signal and a second BPSK modulated signal based on said QPSK signal, and

select between said first phase-shifted signal and said second phase-shifted signal to generate said first BPSK signal and said second BPSK signal.

3. A receiver comprising:

a filter configured to receive a quadrature phase shift keying (“QPSK”) signal;

an amplifier coupled with said filter; and

a QPSK decomposition filter coupled with said amplifier,

said QPSK decomposition filter including:

a mixer configured to generate a mixed signal based on a first phase-shifted signal and a second phase-shifted signal,

said QPSK decomposition filter configured to:

generate a first binary phase shift keying (“BPSK”) modulated signal based on said QPSK signal and a second BPSK modulated signal based on said QPSK signal, and

select between said first phase-shifted signal and said second phase-shifted signal to generate said first BPSK signal and said second BPSK signal.

4. The receiver of claim 1 , further comprising a first BPSK receiver configured to demodulate said first BPSK signal.

5. The receiver of claim 4 , further comprising a second BPSK receiver configured to demodulate said second BPSK signal.

6. A receiver comprising:

a filter configured to receive a quadrature phase shift keying (“QPSK”) signal;

an amplifier coupled with said filter; and

a QPSK decomposition filter coupled with said amplifier,

said QPSK decomposition filter comprising:

a first phase shifter configured to shift a phase of said QPSK signal to generate a first phase-shifted signal;

a second phase shifter configured to shift said phase of said QPSK signal to generate a second phase-shifted signal;

a first switch configured to switch between a first output and a second output to generate a first binary phase shift keying (“BPSK”) signal and a second BPSK signal based on said first phase-shifted signal and said second phase-shifted signal; and

a second switch configured to switch between said first output and said second output to generate said first BPSK signal and said second BPSK signal based on said first phase-shifted signal and said second phase-shifted signal,

said QPSK decomposition filter configured to:

generate a first BPSK modulated signal based on said QPSK signal and a second BPSK modulated signal based on said QPSK signal.

7. The receiver of claim 6 , wherein said QPSK decomposition filter further comprises a switch-control circuit configured to switch said first switch and said second switch between said first output and said second output.

8. The receiver of claim 7 , wherein said switch-control circuit includes a mixer configured to generate a mixed signal based on said first phase-shifted signal and said second phase-shifted signal.

9. The receiver of claim 8 , wherein said switch-control circuit includes a phase detector configured to generate a phase-output signal based on said mixed signal, said first switch and said second switch being configured to switch between said first output and said second output based on said phase-output signal.

10. The receiver of claim 6 , wherein said QPSK decomposition filter further comprises a power divider configured to generate a first channel signal based on said QPSK signal and a second channel signal based on said QPSK signal, wherein said power divider is coupled with said first phase shifter and said second phase shifter.

11. A receiver comprising:

an input filter configured to receive a quadrature phase shift keying (“QPSK”) signal;

an amplifier coupled with said input filter and configured to amplify said QPSK signal; and

a QPSK interlacing filter configured to:

generate a binary phase shift keying (“BPSK”) modulated signal based on said QPSK signal, and

select between a first phase-shifted signal and a second phase-shifted signal, based on a phase of a product of said first phase-shifted signal and said second phase-shifted signal, to generate said BPSK signal.

12. A receiver comprising:

an input filter configured to receive a quadrature phase shift keying (“QPSK”) signal;

an amplifier coupled with said input filter and configured to amplify said QPSK signal; and

a QPSK interlacing filter including:

a first phase shifter configured to generate a first phase-shifted signal with a phase shifted by a positive forty-five degrees from a phase of said QPSK signal, and

a second phase shifter configured to generate a second phase-shifted signal with a phase shifted by a negative forty-five degrees from said phase of said QPSK signal,

said QPSK interlacing filter configured to:

generate a binary phase shift keying (“BPSK”) modulated signal based on said QPSK signal, and

select between said first phase-shifted signal and said second phase-shifted signal to generate said BPSK signal.

13. A receiver comprising:

an input filter configured to receive a quadrature phase shift keying (“QPSK”) signal;

an amplifier coupled with said input filter and configured to amplify said QPSK signal; and

a QPSK interlacing filter including:

a mixer configured to generate a mixed signal based on a first phase-shifted signal and a second phase-shifted signal,

said QPSK interlacing filter configured to:

generate a binary phase shift keying (“BPSK”) modulated signal based on said QPSK signal, and

select between said first phase-shifted signal and said second phase-shifted signal to generate said BPSK signal.

14. The receiver of claim 11 , further comprising a BPSK receiver configured to demodulate said BPSK signal.

15. A receiver comprising:

an input filter configured to receive a quadrature phase shift keying (“QPSK”) signal;

an amplifier coupled with said input filter and configured to amplify said QPSK signal; and

a QPSK interlacing filter comprises including:

a first phase shifter configured to shift a phase of said QPSK signal to generate a first phase-shifted signal;

a second phase shifter configured to shift said phase of said QPSK signal to generate a second phase-shifted signal;

a first switch configured to switch between a first output and a second output to generate a first binary phase shift keying (“BPSK”) signal and a second BPSK signal based on said first phase-shifted signal and said second phase-shifted signal;

a second switch configured to switch between said first output and said second output to generate said first BPSK signal and said second BPSK signal based on said first phase-shifted signal and said second phase-shifted signal; and

a third switch configured to switch between said first output and said second output to generate an output BPSK,

said QPSK interlacing filter configured to:

generate a BPSK modulated signal based on said QPSK signal.

16. The receiver of claim 15 , wherein said QPSK interlacing filter further comprises a switch-control circuit configured to switch said first switch and said second switch between said first output and said second output.

17. The receiver of claim 16 , wherein said switch-control circuit includes a mixer configured to generate a mixed signal based on said first phase-shifted signal and said second phase-shifted signal.

18. The receiver of claim 17 , wherein said switch-control circuit includes a phase detector configured to generate a phase-output signal based on said mixed signal, said first switch and said second switch being configured to switch between said first output and said second output based on said phase-output signal.

19. The receiver of claim 15 , wherein said QPSK interlacing filter further comprises a power divider configured to generate a first channel signal based on said QPSK signal and a second channel signal based on said QPSK signal.

20. The receiver of claim 15 , wherein said QPSK interlacing filter further comprises a third phase shifter configured to shift a second phase of said first BPSK signal and a fourth phase shifter configured to shift a third phase of said second BPSK signal.

21. The receiver of claim 20 , wherein said third switch is configured to select between said first BPSK signal and said second BPSK signal to generate an output BPSK signal.

22. The receiver of claim 2 , further comprising a first BPSK receiver configured to demodulate said first BPSK signal.

23. The receiver of claim 22 , further comprising a second BPSK receiver configured to demodulate said second BPSK signal.

24. The receiver of claim 3 , further comprising a first BPSK receiver configured to demodulate said first BPSK signal.

25. The receiver of claim 24 , further comprising a second BPSK receiver configured to demodulate said second BPSK signal.

26. The receiver of claim 12 , further comprising a BPSK receiver configured to demodulate said BPSK signal.

27. The receiver of claim 13 , further comprising a BPSK receiver configured to demodulate said BPSK signal.