IP Library Granted Patent US 8,582,637
Granted Patent B1
US 8,582,637 · App. 13/754,964 · Granted Nov 12, 2013

Low-complexity, highly-spectrally-efficient communications

Inventor: Amir Eliaz (Moshav Ben Shemen, IL)
Assignee: MagnaCom Ltd.
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Quick Facts
Patent No.
US 8,582,637
App. No.
13/754,964
Granted
Nov 12, 2013
Kind
B1
Abstract

A system may comprise circuitry that includes a sequence estimation circuit and a non-linearity modeling circuit. The circuitry may be operable to receive a single-carrier signal that was generated by passage of symbols through a partial response filter and through a non-linear circuit. The circuitry may be operable to generate estimated values of the symbols using the sequence estimation circuit and using the non-linearity modeling circuit. An output of the non-linearity modeling circuit may be equal to a corresponding input of the non-linearity modeling circuit modified according to a non-linear model that approximates the non-linearity of the non-linear circuit through which the received signal passed.

Claims (52)

1. A method comprising:

in a receiver:

receiving a single-carrier inter-symbol correlated (ISC) signal that was generated by passage of symbols through a non-linear circuit; and

generating estimated values of said symbols using a sequence estimation process and a model of said non-linear circuit, wherein said sequence estimation process comprises:

convolving each one of a plurality of candidate symbol vectors with a plurality of tap coefficients to generate a corresponding one of a plurality of first ISC vectors; and

generating a plurality of metrics, each one of said metrics corresponding to the result of a cost function calculated using one of said first ISC vectors and a second ISC vector.

2. The method of claim 1 , wherein said ISC signal is a partial response signal generated via a partial response filter.

3. The method of claim 1 , wherein said symbols are N-QAM symbols and N is an integer.

4. The method of claim 1 , wherein:

said generating said estimated values of said symbols comprises performing one or more iterations of said sequence estimation process; and

for each iteration of said sequence estimation process, the number of candidate symbol vectors considered is less than the maximum likelihood state space.

5. The method of claim 1 , wherein said plurality of tap coefficients are based on tap coefficients of a partial response filter.

6. The method of claim 5 , wherein said partial response filter comprises two or more filters jointly optimized such that communications between said two or more filters over a channel are more tolerant of non-idealities than communications between a pair of near zero positive ISI filters over said channel.

7. The method of claim 1 , wherein said sequence estimation process comprises:

selecting one of said candidate symbol vectors based on said plurality of metrics; and

outputting a symbol of said selected one of said candidate symbol vectors as one of said estimated values of said symbols.

8. The method of claim 1 , wherein said cost function is based on Euclidean distance.

9. The method of claim 1 , comprising:

generating an inter-symbol correlated feedback signal; and

controlling an equalizer of said receiver based on said feedback signal.

10. The method of claim 9 , comprising generating said inter-symbol correlated feedback signal by applying said model of said non-linear circuit to an inter-symbol correlated signal generated by said sequence estimation process.

11. The method of claim 1 , comprising:

generating an ISC feedback signal by applying said model of said non-linear circuit to an ISC signal generated by said sequence estimation process; and

recovering a carrier frequency of said received single-carrier ISC signal using said ISC feedback signal.

12. A system comprising:

circuitry that includes a sequence estimation circuit and a non-linearity modeling circuit, wherein:

said circuitry is operable to receive an inter-symbol correlated (ISC) signal that carries information bits and that passed through a non-linear circuit;

said information bits are mapped into N-QAM symbols and N is an integer;

said circuitry is operable to generate estimated values of said information bits using said sequence estimation circuit and using said non-linearity modeling circuit; and

an output of said non-linearity modeling circuit is equal to a corresponding input of said non-linearity modeling circuit modified according to a non-linear model that approximates the non-linearity of said non-linear circuit; and

said sequence estimation circuit comprises:

a convolution circuit operable to convolve each one of a plurality of candidate symbol vectors with a plurality of tap coefficients to generate a corresponding one of a plurality of first ISC vectors; and

a metric calculation circuit operable to generate a plurality of metrics, each one of said metrics corresponding to the result of a cost function calculated using one of said first ISC vectors and a second ISC vector.

13. The system of claim 12 , wherein:

said circuitry includes an equalizer;

said equalizer is controlled based on a signal generated via said non-linear modeling circuit.

14. The system of claim 12 , wherein:

said circuitry includes a carrier recovery circuit;

said carrier recovery circuit is controlled based on a signal generated via said non-linear modeling circuit.

15. A receiver comprising:

a partial response filter;

a timing pilot removal circuit;

a non-linearity modeling circuit;

an equalizer that operates based on a first partial response feedback signal;

a carrier recovery circuit that operates based on a second partial response feedback signal; and

a sequence estimation circuit operable to perform a sequence estimation process that comprises:

convolution of each one of a plurality of candidate symbol vectors with a plurality of tap coefficients to generate a corresponding one of a plurality of first inter-symbol correlated (ISC) vectors; and

generation of a plurality of metrics, each one of said metrics corresponding to the result of a cost function calculated using one of said first ISC vectors and a second ISC vector.

16. The receiver of claim 15 , comprising an N-QAM de-mapper, where N is an integer.

17. The receiver of claim 15 wherein said non-linearity modeling circuit is configured to model:

non-linearity in a transmitter from which said receiver is configured to receive a communication; and/or

non-linearity in said receiver.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2017
From: MAGNACOM LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041604/0861 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2013
From: ELIAZ, AMIR
To: MAGNACOM LTD.
Reel/Frame 030038/0636 →
Continuity (4)
Provisional Application 61662085 · Jun 20, 2012
Provisional Application 61726099 · Nov 14, 2012
Provisional Application 61729774 · Nov 26, 2012
Provisional Application 61747132 · Dec 28, 2012