Decision feedback equalizer with multiple cores for highly-spectrally-efficient communications
One or more embodiments describe a decision feedback equalizer with multiple cores for highly spectrally efficient communications. An equalization circuit in a receiver may include a decision feedback equalizer circuit having a first plurality of tap coefficients that are determined based on a cost function that receives as input an error signal that is an inter-symbol-correlated (ISC) signal. The decision feedback equalizer circuit may further include a second plurality of tap coefficients that are determined based on a filter with an ISC response. The cost function may determine the mean square of the error signal. The cost function is constrained or unconstrained. The error signal may represents error caused by a channel. In some embodiments, the ISC signal may be a partial response signal, and the filter with an ISC response may be a partial response filter.
1. An equalization circuit in a receiver, the circuit comprising:
decision feedback equalizer circuit having a first plurality of tap coefficients that adapt during operation of the receiver to compensate for channel distortions; and
a second plurality of tap coefficients that:
are initialized to replicate a response corresponding to filter of the receiver and a filter of a transmitter from which the receiver receives signals;
are occasionally or periodically calibrated, during operation of the receiver, to replicate the response corresponding to the filter of the receiver and the filter of the transmitter; and
do not adapt to compensate for channel distortions.
2. The equalization circuit of claim 1 , wherein the adaptation of the first plurality of tap coefficients is based on a cost function.
3. The equalization circuit of claim 2 , wherein the cost function is constrained.
4. The equalization circuit of claim 1 , wherein the decision feedback equalizer circuit receives as input an error signal generated based on symbol estimates determined by a sequence estimation circuit of the receive.
5. The equalization circuit of claim 4 , wherein the error signal is generated via processing of the symbol estimates determined by the sequence estimation circuit.
6. The equalization circuit of claim 5 , wherein the error signal is a partial response signal generated via a convolution of the symbol estimates and tap coefficients based on the response corresponding to the filter of the receiver and the filter of the transmitter.
7. The equalization circuit of claim 1 , wherein the second plurality of tap coefficients are used by a sequence estimation circuit that uses the second plurality of tap coefficients to detect symbols that are encoded in an input signal to the receiver.
8. The equalization circuit of claim 1 , wherein the second plurality of tap coefficients are stored in coefficient registers.
9. The equalization circuit of claim 1 , further comprising tap update circuitry that performs the adaptation of the first plurality of tap coefficients wherein the adaptation of the first plurality of tap coefficients is based on symbol error rate in the receiver.
10. The equalization circuit of claim 9 , wherein the tap update circuitry receives a set of error vector(s), each error vector in the set representing the difference between a vector of estimated symbols generated in the receiver and a vector of expected symbols, and wherein the tap update circuitry uses the error vector(s) to update the second plurality of tap coefficients to minimize symbol error rate in the receiver.
11. The equalization circuit of claim 1 , wherein an output of the decision feedback equalizer circuit is mixed with an output of a feed forward equalizer.
12. A method comprising:
in a receiver, processing a received signal, wherein the processing comprises:
adapting, during operation of the receiver, a first plurality of tap coefficients based on distortion in a channel over which the receiver is receiving the received signal;
initializing a second plurality of tap coefficients to replicate a response corresponding to a filter of the receiver and to a filter of a transmitter from which the receiver is receiving the received signal; and
occasionally or periodically calibrating, during operation of the receiver, the second plurality of tap coefficients to replicate the response corresponding to the filter of the receiver and the filter of the transmitter, wherein said second plurality of tap coefficients are not adapted based on the distortion in the channel over which the receiver is receiving the received signal.
13. The method of claim 12 , comprising adapting the first plurality of tap coefficients based on a cost function.
14. The method of claim 13 , wherein the cost function is constrained.
15. The method of claim 12 , wherein the processing is based on an error signal that is generated based on symbol estimates determined by a sequence estimation circuit of the receiver.
16. The method of claim 15 , wherein the error signal is generated via processing of the symbol estimates determined by the sequence estimation circuit.
17. The method of claim 16 , wherein the error signal is a partial response signal generated via a convolution of the symbol estimates and tap coefficients based on the response corresponding to the filter of the receiver and the filter of the transmitter.
18. The method of claim 12 , wherein the second plurality of tap coefficients are used by a sequence estimation circuit that uses the second plurality of tap coefficients to detect symbols that are encoded in an input signal to the receiver.
19. The method of claim 12 , wherein the second plurality of tap coefficients are stored in coefficient registers.
20. The method of claim 1 , wherein:
the receiver comprises tap update circuitry that performs the adapting of the first plurality of tap coefficients; and
the adaptating of the first plurality of tap coefficients is based on symbol error rate in the receiver.
21. The method of claim 20 , wherein the tap update circuitry receives a set of error vector(s), each error vector in the set representing the difference between a vector of estimated symbols generated in the receiver and a vector of expected symbols, and wherein the tap update circuitry uses the error vector(s) to update the second plurality of tap coefficients to minimize symbol error rate in the receiver.
22. The equalization circuit of claim 1 , comprising mixing an output of the decision feedback equalizer circuit with an output of a feed forward equalizer of the receiver.