IP Library Granted Patent US 8,571,146
Granted Patent B1
US 8,571,146 · App. 13/755,054 · Granted Oct 29, 2013

Method and system for corrupt symbol handling for providing high reliability sequences

Inventor: Amir Eliaz (Moshav Ben Shemen, IL)
Assignee: MagnaCom Ltd.
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Quick Facts
Patent No.
US 8,571,146
App. No.
13/755,054
Granted
Oct 29, 2013
Kind
B1
Abstract

For corrupt symbol handling for providing high reliability sequences, an inter-symbol correlated (ISC) signal is received. During sequence estimation when demodulating the received ISC signal, partial response samples in the ISC may be processed utilizing an erasure mechanism. The partial response samples are spread (e.g. interleaved) over time during modulation by a modulator. A determination is made as to whether to utilize self erasure or external erasure to process the spread partial response samples. The determination may be based on whether or not events of low SNR for corresponding ones of the partial response samples are identified. The external erasure may be utilized for processing the corresponding ones of the partial response samples when the events of low SNR are identified and the self erasure is utilized when the events of low SNR are not identifiable. Erasure results maybe fed back to the modulator.

Claims (41)

1. A method, comprising:

receiving an inter-symbol correlated (ISC) signal;

demodulating said received signal, said demodulating comprising:

generating a vector of estimated transmitted symbols corresponding to said ISC signal; and

processing said inter-symbol correlated signal utilizing an erasure mechanism that comprises:

determining whether an equalizer can identify an event of low signal-to-noise ratio (SNR) corresponding to one or more elements of said estimated transmitted symbols vector; and

utilizing one of self erasure or external erasure based on whether said equalizer can identify said event of low SNR for erasing said one or more elements of said estimated transmitted symbols vector, wherein said self erasure is utilized for said erasing when said event of low SNR cannot be identified by said equalizer.

2. The method according to claim 1 , wherein said inter-symbol correlated signal comprises partial response samples.

3. The method according to claim 1 , wherein said ISC signal was generated by:

mapping bit sequences to symbols;

processing said symbols via a partial response pulse shaping filter to generate partial response samples;

spreading said partial response samples over time via an interleaver; and

processing said spread partial response samples via a re-shaping filter.

4. The method according to claim 1 , comprising feeding back results corresponding to said erasure mechanism to a modulator that transmitted said inter-symbol correlated signal, such that said modulator is enabled to adjust operation of one or more functions and/or components based on said feedback results.

5. The method according to claim 1 , comprising utilizing one of said self erasure or said external erasure for said erasing based on a user configuration for concurrent operation of self erasure and external erasure.

6. The method according to claim 1 , wherein said external erasure is utilized for said erasing when said event of low SNR can be identified by said equalizer.

7. The method according to claim 1 , comprising:

determining said one or more elements of said estimated transmitted symbols vector based on one or more branch metrics.

8. The method according to claim 1 , wherein:

said erasing comprises iteratively attempting to locate said one or more elements of said estimated transmitted symbols vector.

9. The method according to claim 1 , comprising determining, by said equalizer, that said one or more elements of said estimated transmitted symbols vector corresponds to a low signal-to-noise ratio (SNR) event.

10. A system, comprising:

one or more circuits for use in a demodulator, said one or more circuits being operable to:

receive an inter-symbol correlated (ISC) signal;

generate a vector of estimated transmitted symbols corresponding to said ISC signal; and

demodulate said received signal, said demodulation comprising processing of said inter-symbol correlated signal utilizing an erasure mechanism that comprises:

determination of whether an equalizer can identify an event of low signal-to-noise ratio (SNR) corresponding to one or more elements of said estimated transmitted symbols vector; and

utilizing one of self erasure or external erasure based whether said equalizer can identify said event of low SNR for erasure of one or more elements of said estimated transmitted symbols vector, wherein said self erasure is utilized for said erasure when said event of low SNR cannot be identified by said equalizer.

11. The system according to claim 10 , wherein said inter-symbol correlated signal comprises partial response samples.

12. The system according to claim 10 , wherein said ISC signal was generated by a transmitter:

mapping bit sequences to symbols;

processing said symbols via a partial response pulse shaping filter to generate partial response samples;

spreading said partial response samples over time via an interleaver of said transmitter; and

processing said spread partial response samples via a re-shaping filter.

13. The system according to claim 10 , wherein said one or more circuits are operable to feed back results corresponding to said erasure mechanism to a modulator that transmitted said inter-symbol correlated signal, such that said modulator is enabled to adjust operation of one or more functions and/or components based on said feedback results.

14. The system according to claim 10 , wherein said one or more circuits are operable to utilize one of said self erasure or said external erasure for said erasure of said one or more elements of said estimated transmitted symbols vector based on a user configuration for concurrent operation of self erasure and external erasure.

15. The system according to claim 10 , wherein said external erasure is utilized for said erasing when said event of low SNR are can be identified by said equalizer.

16. The system according to claim 10 , wherein said one or more circuits are operable to:

determine said one or more elements of said estimated transmitted symbols vector based on one or more branch metrics.

17. The system according to claim 10 , wherein:

said erasure of said one or more elements of said estimated transmitted symbols vector comprises iteratively attempting to locate said one or more elements of said estimated transmitted symbols vector.

Assignments (4)
CORRECTIVE ASSIGNMENT TO CORRECT THE EXECUTION DATE PREVIOUSLY RECORDED AT REEL: 047422 FRAME: 0464. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 6, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 048883/0702 →
MERGER Recorded Oct 5, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047422/0464 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2017
From: MAGNACOM LTD.
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041604/0861 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 19, 2013
From: ELIAZ, AMIR
To: MAGNACOM LTD.
Reel/Frame 030038/0636 →
Continuity (4)
Provisional Application 61662085 · Jun 20, 2012
Provisional Application 61726099 · Nov 14, 2012
Provisional Application 61729774 · Nov 26, 2012
Provisional Application 61747132 · Dec 28, 2012