Low power current comparator for switched mode regulator

1. A switched mode regulator comprising

a feedback clamp stage receiving a current input; and

a current limited inverting amplifier stage coupled to the feedback clamp stage, the current limited inverting amplifier stage including:

a first PMOS transistor having a source coupled to V DD , a drain and a gate;

a second PMOS transistor having a source coupled to V DD , a drain and a gate;

a third PMOS transistor having a source coupled to V DD , a drain and a gate;

a fourth PMOS transistor having a source coupled to V DD , a drain and a gate; and

a first NMOS transistor having a drain coupled to the drain of the first PMOS transistor to form an output. a gate and a source;

wherein the current limited inverting amplifier stage outputs a low voltage value when current flows into the current input and a high voltage value when current flows out of the current input.

2. The switched mode regulator of claim 1 further comprising a voltage reference input to the current limited inverting amplifier stage, the current limited inverting amplifier stage controlling a voltage of the current input as a function of the voltage reference.

3. The switched mode regulator of claim 1 wherein the current limited inverting amplifier stage comprises a level-shifted common source NMOS inverting amplifier.

4. The switched mode regulator of claim 1 wherein the current limited inverting amplifier stage comprises a differential inverting gain stage.

5. The switched mode regulator of claim 1 wherein the current limited inverting amplifier stage comprises a differential current mirror amplifier.

6. The switched mode regulator of claim 1 wherein the current limited inverting amplifier stage comprises:

a first bias current source having an input coupled to the source of the first NMOS transistor and an output coupled to V SS ;

a second bias current source coupled to the feedback clamp stage; and

a second NMOS transistor having a drain coupled to the feedback clamp stage to form an output, a source coupled to V SS and a gate coupled to the source of the first NMOS transistor.

7. The switched mode regulator of claim 1 wherein the feedback clamp stage comprises:

a first NMOS transistor having a drain coupled to V DD , a source and a gate; and

a first PMOS transistor having a source coupled to the source of the first NMOS transistor to form an input, a drain coupled to V SS and a gate coupled to the gate of the first NMOS transistor.

8. The switched mode regulator of claim 1 wherein the current limited inverting amplifier stage further comprises a second NMOS transistor having a drain coupled to the drain of the second PMOS transistor, a gate coupled to a reference voltage and a source.

9. The switched mode regulator of claim 8 wherein the current limited inverting amplifier stage further comprises a first bias current source having an input coupled to the source of the first NMOS transistor and the source of the second NMOS transistor and an output coupled to V SS .

10. The switched mode regulator of claim 1 further comprising a second NMOS transistor having a drain coupled to the drain of the second PMOS transistor, a gate coupled to the gate of the first NMOS transistor and a source.

11. The switched mode regulator of claim 10 further comprising a third NMOS transistor having a drain coupled to the drain of the third PMOS transistor, a gate coupled to the input and a source.

12. The switched mode regulator of claim 11 further comprising a fourth NMOS transistor having a drain coupled to the drain of the fourth PMOS transistor, a gate coupled to a reference voltage and a source.

13. The switched mode regulator of claim 12 further comprising a first bias current source having an input coupled to the source of the third NMOS transistor and the source of the fourth NMOS transistor and an output coupled to V SS .

14. A switched mode regulator comprising:

a first NMOS transistor having a drain coupled to V DD , a source and a gate;

a first PMOS transistor having a source coupled to the source of the first NMOS transistor to form an input, a drain coupled to V SS and a gate coupled to the gate of the first NMOS transistor;

a second NMOS transistor having a chain coupled to V DD , a source and a gate coupled to the input;

a first bias current source having an input coupled to the source of the second NMOS transistor and an output coupled to V SS ;

a second bias current source having an input coupled to the drain of the first NMOS transistor and an output coupled to the gate of the first NMOS transistor; and

a third NMOS transistor having a drain coupled to the gate of the first NMOS transistor to form an output, a source coupled to V SS and a gate coupled to the source of the second NMOS transistor.

15. A switched mode regulator comprising:

a first NMOS transistor having a drain coupled to V DD , a source and a gate;

a first PMOS transistor having a source coupled to the source of the first NMOS transistor to form an input, a drain coupled to V SS and a gate coupled to the gate of the first NMOS transistor;

a second PMOS transistor having a source coupled to V DD , a drain and a gate; and

a third PMOS transistor having a source coupled to V DD , a drain and a gate coupled to the gate of the second PMOS transistor and to the drain of the third PMOS transistor.

16. The switched mode regulator of claim 15 further comprising a second NMOS transistor having a drain coupled to the drain of the second PMOS transistor, a gate coupled to the input and a source.

17. The switched mode regulator of claim 16 further comprising a third NMOS transistor having a drain coupled to the drain of the third PMOS transistor, a gate coupled to a reference voltage and a source.

18. The switched mode regulator of claim 17 further comprising a first bias current source having an input coupled to the source of the second NMOS transistor and the source of the third NMOS transistor and an output coupled to V SS .