Encoding and decoding in flash memories using convolutional-type low-density parity check codes
View Patent ↗Methods and apparatus are provided for encoding and decoding in flash memories using convolutional-type low parity density check codes. A plurality of bits to be stored on a flash memory device are encoded using a convolutional-type low density parity check code, such as a spatially coupled low density parity check code. The encoded pages or portions thereof can be decoded independently of other pages. In one embodiment, an encoded page is decoded jointly with one or more additional pages in the same wordline or a different wordline.
1. A method for encoding data for storage on a flash memory device, comprising:
obtaining a plurality of bits to be stored on said flash memory device; and
encoding said plurality or bits for storage as a page on said flash memory device using a convolutional-type low density parity check code.
2. The method of claim 1 , further comprising the step of storing said encoded page on said flash memory device.
3. The method of claim 1 , wherein said convolutional-type low density parity check code comprises a spatially coupled low density parity check code.
4. The method of claim 1 , wherein said encoded page is decoded independently of other pages.
5. The method of claim 1 , wherein a portion of said encoded page is decoded independently of other pages.
6. The method of claim 1 , wherein said encoded page is decoded jointly with one or more additional pages in a wordline of said flash memory device.
7. The method of claim 1 , wherein said encoded page is decoded jointly with one or more additional pages in at least one additional wordline of said flash memory device.
8. The method of claim 1 , further comprising the step of encoding a plurality of pages in a wordline of said flash memory device in an incremental manner as user data becomes available by saving an encoder state until desired pages are encoded.
9. The method of claim 1 , wherein said encoding step further comprises the step of encoding one or more parity bits in a parity area of said page, and wherein a portion of said parity area for at least one page of a given wordline is allocated for parity bits for at least one other page of said given wordline based on relative error probabilities of said pages.
10. A tangible machine-readable recordable storage medium for encoding data for storage on a flash memory device, wherein one or more software programs when executed by one or more processing devices implement the steps of the method of claim 1 .
11. A flash memory system, comprising:
one or more encoders for encoding a plurality of bits to be stored on a flash memory device using a convolutional-type low density parity check code.
12. The flash memory system of claim 11 , further comprising a flash storage medium storing said encoded page on said flash memory device.
13. The flash memory system of claim 11 , wherein said convolutional-type low density parity check code comprises a spatially coupled low density parity check code.
14. The flash memory system of claim 11 , wherein said encoded page is decoded independently of other page.
15. The flash memory system of claim 11 , wherein a portion of said encoded page is decoded independently of other pages.
16. The flash memory system of claim 11 , wherein said encoded page is decoded jointly with one or more additional pages in a wordline of said flash memory device.
17. The flash memory system of claim 11 , wherein said encoded page is decoded jointly with one or more additional pages in at least one additional wordline of said flash memory device.
18. The flash memory system of claim 11 , wherein one or more of said encoders encode a plurality of pages in a wordline of said flash memory device in an incremental manner as user data becomes available by saving an encoder state until desired pages are encoded.
19. The flash memory system of claim 11 , wherein one or more of said encoders encode one or more parity bits in a parity area of said page, and wherein a portion of said parity area for at least one page of a given wordline is allocated for parity bits for at least one other page of said given wordline based on relative error probabilities of said pages.
20. The flash memory system of claim 11 , wherein said flash memory device comprises a plurality of cells each capable of storing at least two data levels per cell.