CIRCUIT TESTING ARRANGEMENT FOR SERIALISER/DESERIALISER
The present invention relates to a test arrangement for a serdes ip block and in particular provides a serdes test chip comprising a serdes instance to be tested and further instances of said serdes, said further instances constitution a data transfer path for data with which said serdes is to be tested. The data may come from a programmable gate array and enables the testing of data transfer schemes yet to be embodied in an integrated circuit ip block.
1 . A serdes test chip comprising a serdes instance to be tested and further instances of said serdes, said further instances constituting a data transfer path for data with which said serdes is tested.
2 . A test chip as claimed in claim 1 wherein the data from said further instances is multiplexed together to provide said data with which said serdes is tested.
3 . A test chip as claimed in claim 2 including circuitry for realigning data from said further instances before multiplexing.
4 . A test chip as claimed in claim 1 including two instances of said serdes for testing via loopback.
5 . A test chip as claimed in claim 1 enabling testing of data transfer schemes yet to be embodied in an integrated circuit ip block.
6 . A serdes test arrangement including a test chip as claimed in claim 1 .
7 . The arrangement of claim 6 including a pattern generator, said data path being part of an interface with said pattern generator.
8 . The arrangement of claim 7 wherein the pattern generator is embodied in a programmable gate array.
9 . The arrangement of claim 7 including sufficient instances of serdes that are slower speed than said serdes to be tested to transfer of data via said data path to enable testing of said serdes to be tested at faster speed.