OCTAL CLOCK PHASE INTERPOLATOR ARCHITECTURE
The present invention provides an apparatus and method of generating a set of 8 clock signals nominally spaced at equal 45° intervals by phase interpolation from a set of 4 quadrature reference clocks. The scheme is useful for clock generation for data capture in an oversampled clock/data recovery (CDR) system where the frequency of data sampling is twice that of the frequency of reference clock edges.
1 . A clock phase generating circuit for generating a set of eight clock phases for a clock/data recovery application, comprising:
a rotating first stage interpolator; and
a pair of fixed-phase second stage interpolators;
wherein the rotating first stage interpolator is coupled to the pair of fixed-phase second stage interpolators to generate two interleaved sets of quadrature clocks.
2 . A clock phase generating circuit as according to claim 1 , wherein the order of bias signals to one of said second stage interpolators is reversed causing its output clocks to be rotated by 22.5° in the opposite direction to that of said other one of the second stage interpolators, thereby establishing a 45° phase shift between the first and second interpolator clock outputs.
3 . A clock phase generating circuit as in claim 1 , further comprising phase setting adjustment means for rotating the phase of the second stage interpolators in opposite directions.
4 . A clock phase generating circuit as in claim 1 , further comprising bias control adjustment means for adjustment of the phase setting of said second stage interpolators to adjust the timings between the clocks output from the two second stage interpolators.
5 . An octal clock phase interpolator comprising:
a clock phase generating means for generating a set of eight clock phases for a clock/data recovery application, comprising:
a rotating first stage interpolator; and
a pair of fixed-phase second stage interpolators;
wherein the rotating first stage interpolator is coupled to the pair of fixed-phase second stage interpolators to generate two interleaved sets of quadrature clocks.
6 . A receiver-side circuit comprising:
an octal clock phase interpolator comprising:
a clock phase generating means for generating a set of eight clock phases for a clock/data recovery application, comprising:
a rotating first stage interpolator; and
a pair of fixed-phase second stage interpolators;
wherein the rotating first stage interpolator is coupled to the pair of fixed-phase second stage interpolators to generate two interleaved sets of quadrature clocks.
7 . A clock phase generating circuit for generating a set of eight clock phases for a clock/data recovery application, comprising:
a rotating first stage interpolator;
a pair of fixed-phase second stage interpolators;
wherein the rotating first stage interpolator is coupled to the pair of fixed-phase second stage interpolators to generate two interleaved sets of quadrature clocks; and
bias control adjustment means for adjustment of the phase setting of said second stage interpolators to adjust the timings between the clocks output from the two second stage interpolators.
8 . An octal clock phase interpolator comprising:
a clock phase generating means for generating a set of eight clock phases for a clock/data recovery application, comprising:
a rotating first stage interpolator; and
a pair of fixed-phase second stage interpolators;
wherein the rotating first stage interpolator is coupled to the pair of fixed-phase second stage interpolators to generate two interleaved sets of quadrature clocks; and
wherein the order of bias signals to one of said second stage interpolators is reversed causing its output clocks to be rotated by 22.5° in the opposite direction to that of said other one of the second stage interpolators, thereby establishing a 45° phase shift between the first and second interpolator clock outputs.
9 . A receiver-side circuit comprising:
an octal clock phase interpolator comprising:
a clock phase generating means for generating a set of eight clock phases for a clock/data recovery application, comprising:
a rotating first stage interpolator; and
a pair of fixed-phase second stage interpolators;
wherein the rotating first stage interpolator is coupled to the pair of fixed-phase second stage interpolators to generate two interleaved sets of quadrature clocks; and
wherein the order of bias signals to one of said second stage interpolators is reversed causing its output clocks to be rotated by 22.5° in the opposite direction to that of said other one of the second stage interpolators, thereby establishing a 45° phase shift between the first and second interpolator clock outputs.