IP Library Granted Patent US 9,147,650
Granted Patent B2
US 9,147,650 · App. 13/755,881 · Granted Sep 29, 2015

Semiconductor device, method for manufacturing semiconductor device, and electronic apparatus

Inventors: Yoshiya Hagimoto (Kanagawa, JP); Nobutoshi Fujii (Kanagawa, JP); Kenichi Aoyagi (Kanagawa, JP)
Assignee: Sony Corporation
H01L23/498H01L21/76829H01L21/76849H01L21/76885H01L23/49866H01L24/03H01L24/05H01L24/08H01L24/80H01L25/0657H01L25/50H01L27/1464H01L27/14634H01L2224/03845H01L2224/05026H01L2224/05147H01L2224/05562H01L2224/05666H01L2224/05681H01L2224/081H01L2224/08147H01L2224/08501H01L2224/09181H01L2224/80895H01L2225/06524H01L2924/00014H01L2924/13091H01L2924/15321H01L2924/15331
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,147,650
App. No.
13/755,881
Granted
Sep 29, 2015
Kind
B2
Abstract

There is provided a semiconductor device, including a semiconductor substrate, an interlayer insulating layer formed on the semiconductor substrate, a bonding electrode formed on a surface of the interlayer insulating layer, and a metal film which covers an entire surface of a bonding surface including the interlayer insulating layer and the bonding electrode.

Claims (50)

1. A semiconductor device, comprising:

a semiconductor substrate;

an interlayer insulating layer formed on the semiconductor substrate;

a bonding electrode formed in a surface of the interlayer insulating layer; and

a metal film layer which covers an entire surface of a planar bonding surface including the interlayer insulating layer and the bonding electrode, the metal film layer including an insulating film portion covering the interlayer insulating layer and a metal film portion covering the bonding electrode,

wherein the insulating film portion is a reaction product of a metal material of the metal film layer with the interlayer insulating layer.

2. The semiconductor device according to claim 1 ,

wherein the metal film layer includes at least one type selected from Ta or Ti.

3. The semiconductor device according to claim 1 , further comprising a barrier surface layer between the interlayer insulating layer and the bonding electrode.

4. The semiconductor device according to claim 1 , wherein a thickness of the metal film layer is equal to or less than 100 nm.

5. The semiconductor device according to claim 4 , wherein the thickness of the metal film layer is equal to or less than 20 nm.

6. A semiconductor device including a first semiconductor substrate and a second semiconductor substrate which are formed by laminating surfaces of bonding electrodes through metal films, the semiconductor device comprising:

the first semiconductor substrate;

a first interlayer insulating layer formed on the first semiconductor substrate;

a first bonding electrode formed in a surface of the first interlayer insulating layer;

the second semiconductor substrate bonded to the first semiconductor substrate;

a second interlayer insulating layer formed on the second semiconductor substrate;

a second bonding electrode formed in a surface of the second interlayer insulating layer;

a metal film formed on a bonding surface between the first semiconductor substrate and the second semiconductor substrate, and between the first bonding electrode and the second bonding electrode; and

an insulating film which is formed on the bonding surface between the first semiconductor substrate and the second semiconductor substrate, and on a part in contact with the first interlayer insulating layer or the second interlayer insulating layer, and which includes a reaction product between the metal film and the first interlayer insulating layer or the second interlayer insulating layer.

7. The semiconductor device according to claim 6 , further comprising:

a first metal film formed on the first bonding electrode of the first semiconductor substrate;

a first insulating film which is formed on the first interlayer insulating layer, and which includes a reaction product between the first metal film and the first interlayer insulating layer or the second interlayer insulating layer;

a second metal film formed on the second bonding electrode of the second semiconductor substrate; and

a second insulating film which is formed on the second interlayer insulating layer, and which includes a reaction product between the second metal film and the first interlayer insulating layer or the second interlayer insulating layer.

8. An electronic apparatus comprising:

the semiconductor device according to claim 6 ; and

a signal processing circuit which processes an output signal of the semiconductor device.

9. The electronic apparatus according to claim 8 , further comprising:

a first metal film formed on the first bonding electrode of the first semiconductor substrate;

a first insulating film which is formed on the first interlayer insulating layer, and which includes a reaction product between the first metal film and the first interlayer insulating layer or the second interlayer insulating layer;

a second metal film formed on the second bonding electrode of the second semiconductor substrate; and

a second insulating film which is formed on the second interlayer insulating layer, and which includes a reaction product between the second metal film and the first interlayer insulating layer or the second interlayer insulating layer.

10. The semiconductor device according to claim 6 , wherein the bonding surface is a planar surface.

11. The semiconductor device according to claim 6 , further comprising

a first barrier surface layer between the first interlayer insulating layer and the first bonding electrode, and

a second barrier surface layer between the second interlayer insulating layer and the second bonding electrode.

12. An electronic apparatus, comprising:

a semiconductor device which includes

a semiconductor substrate,

an interlayer insulating layer formed on the semiconductor substrate,

a bonding electrode formed in a surface of the interlayer insulating layer, and

a metal film layer which covers an entire surface of a planar bonding surface including the interlayer insulating layer and the bonding electrode, the metal film layer including an insulating film portion covering the interlayer insulating layer and a metal film portion covering the bonding electrode,

wherein the insulating film portion is a reaction product of a metal material of the metal film layer with the interlayer insulating layer; and

a signal processing circuit which processes an output signal of the semiconductor device.

13. The electronic apparatus according to claim 12 ,

wherein the metal film layer includes at least one type selected from Ta or Ti.

14. The electronic apparatus according to claim 12 , further comprising a barrier surface layer between the interlayer insulating layer and the bonding electrode.

15. The electronic apparatus according to claim 12 , wherein a thickness of the metal film layer is equal to or less than 100 nm.

16. The electronic apparatus according to claim 15 , wherein the thickness of the metal film layer is equal to or less than 20 nm.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2013
From: HAGIMOTO, YOSHIYA; FUJII, NOBUTOSHI; AOYAGI, KENICHI
To: SONY CORPORATION
Reel/Frame 029741/0319 →
Priority Claims (1)
JP 2012-029429 · Feb 14, 2012 · national
Continuity (1)
Related Publication 20130207271A1 · Aug 15, 2013