Low power and compact area digital integrator for a digital phase detector

1. A phase-locked loop circuit for receiving a reference signal including a reference phase and generating a source signal including a source phase related to the reference phase, the phase-locked loop circuit comprising:

a first circuitry configured to:

receive the reference signal and the source signal, and

generate a correction signal for demonstrating a difference in phase between the reference signal and the source signal;

a second circuitry configured to:

receive the correction signal, and

generate a digital signal for demonstrating a phase-to-digital conversion of the correction signal;

a third circuitry configured to:

receive the digital signal, and

generate a control signal for demonstrating a converted value of the digital signal;

a fourth circuitry configured to:

receive the control signal, and

generate the source signal in response to the control signal; and

a digital window comparator configured to:

receive the digital signal,

compare a characteristic of the digital signal to a low threshold and a high threshold of a range that includes an achievable voltage that the phase-locked loop has an ability to deliver to achieve phase-lock, and

generate a lock signal for indicating that the characteristic of the digital signal is outside of the range.

2. The phase-locked loop circuit of claim 1 , wherein the second circuitry is further configured to decimate the digital signal.

3. The phase-locked loop circuit of claim 1 , wherein the second circuitry is further configured to down-sample the digital signal.

4. The phase-locked loop circuit of claim 1 , wherein the second circuitry is further configured to decimate and down-sample the digital signal.

5. The phase-locked loop circuit of claim 1 , wherein the second circuitry includes a continuous-time sigma-delta modulator.

6. The phase-locked loop circuit of claim 1 , wherein:

the third circuitry includes an accumulator and a digital-to-analog converter, and

the control signal includes a converted voltage of a digital word generated by the accumulator from the digital signal.

7. The phase-locked loop circuit of claim 1 , wherein the first circuitry includes a phase detector configured to generate the binary or digital correction signal.

8. The phase-locked loop circuit of claim 1 , wherein:

the third circuitry includes an accumulator,

the control signal includes a digital word generated by the accumulator from the digital signal, and

the fourth circuitry includes a digitally-controlled oscillator configured to generate the source signal in response to the digital word.

9. The phase-locked loop circuit of claim 1 , wherein the fourth circuitry includes a voltage-controlled oscillator.

10. A method of generating a source signal from a reference signal including a reference phase, the source signal including a source phase related to the reference phase, the method comprising:

receiving the reference signal and the source signal;

generating a correction signal communicating a difference in phase between the reference signal and the source signal;

generating a digital signal communicating a phase-to-digital conversion of the correction signal;

generating a control signal communicating a converted value of the digital signal;

generating the source signal in response to the control signal;

comparing a characteristic of the digital signal to a low threshold and a high threshold of a range that includes an achievable voltage that the phase-locked loop has an ability to deliver to achieve phase-lock; and

generating a lock signal for indicating that the characteristic of the digital signal is outside of the range.

11. The method of claim 10 , wherein generating the digital signal includes decimating the correction signal.

12. The method of claim 10 , wherein generating the digital signal includes down-sampling the correction signal.

13. The method of claim 10 , wherein generating the digital signal includes decimating and down-sampling the correction signal.

14. The method of claim 10 , wherein the phase-to-digital conversion of the correction signal includes continuous-time sigma-delta modulation of the correction signal.

15. The method of claim 10 , wherein the correction signal includes a binary correction signal or a digital correction signal.

16. The method of claim 10 , wherein generating the control signal includes digital-to-analog conversion of the digital signal.

17. A phase-locked loop circuit for receiving a reference signal including a reference phase and generating a source signal including a source phase related to the reference phase, the phase-locked loop circuit comprising:

means for generating a correction signal for communicating a difference in phase between the reference signal and the source signal;

means for generating a digital signal for communicating phase-to-digital conversion of the correction signal;

means for generating a control signal for communicating a converted value of the digital signal;

means for generating the source signal in response to the control signal;

means for comparing a characteristic of the digital signal to a low threshold and a high threshold of a range that includes an achievable voltage that the phase-locked loop has an ability to deliver to achieve phase-lock; and

means for generating a signal for indicating that the characteristic of the digital signal is outside of the range.