Granted Patent B2

US 9,078,100 · App. 13/758,366 · Granted Jul 7, 2015

Abstract

Claims (59)

1. A system comprising:

a first circuit operable to demodulate up to N channels of a signal from a direct broadcast satellite (DBS) low-noise block downconverter (LNB), such that said first circuit is operable to output up to N demodulated channels to one or more client devices; and

an expansion interface circuit via which a second circuit is operable to demodulate up to M channels of said signal from said DBS LNB for output to one or more client device;

wherein, when said second circuit is installed in a satellite reception assembly, said system is operable to output up to M+N demodulated channels to one or more client devices.

2. The system of claim 1 , wherein said first circuit and said expansion interface circuit are enclosed in a shared housing.

3. The system of claim 2 , wherein said housing is mounted to a satellite reception assembly.

4. The system of claim 1 , comprising:

an aggregation circuit operable to combine up to N demodulated channels from said first circuit with up to M demodulated channels from said second circuit onto a single coaxial cable for output to one or more client devices.

5. A system comprising:

a first digital processing circuit comprising a first expansion interface circuit, where:

said first digital processing circuit is operable to:

accept, as input, a digitized and downconverted version of a received direct broadcast satellite (DBS) signal;

select a first plurality of channels of said digitized and downconverted version of said DBS signal;

process one of said selected first plurality of channels to generate a second signal; and

output said downconverted and digitized version of said DBS signal, said selected first plurality of channels, and/or said second signal via said first expansion interface circuit.

6. The system of claim 5 ,

comprising a second digital processing circuit;

said second digital processing circuit comprising a second expansion interface circuit that is coupled to said first expansion interface circuit;

said second digital processing circuit is operable to:

select a second plurality of channels of said downconverted and digitized version of said DBS signal;

process one of said selected second plurality of channels to generate a third signal; and

output said downconverted and digitized version of said DBS signal, said selected second plurality of channels, and/or said third signal via said second expansion interface circuit.

7. The system of claim 6 , comprising:

a first interface circuit operable to transmit said second signal in accordance with one or more networking and/or multimedia standards;

a second interface circuit operable to transmit said third signal in accordance with one or more networking and/or multimedia standards; and

an aggregation circuit operable to:

combine a signal output by said first interface circuit with a signal output by said second interface circuit to generate a fourth circuit; and

transmit said fourth circuit to a client device in accordance with one or more networking and/or multimedia standards.

8. The system of claim 7 , wherein said aggregation circuit is operable to frequency division multiplex said signal output by said first interface circuit and said signal output by said second interface circuit onto a communication link.

9. The system of claim 6 , wherein said first digital processing circuit is operable to demodulate said one of said selected first plurality of channels to recover an MPEG transport stream.

10. The system of claim 9 , wherein said second digital processing circuit is operable to demodulate said one of said selected second plurality of channels to recover an MPEG transport stream.

11. The system of claim 6 , wherein:

said first digital processing circuit is part of a first module residing on a first substrate;

said second digital processing circuit is part of a second module residing on a second substrate; and

said first module and said second module are enclosed in a shared housing.

12. The system of claim 11 , wherein said housing is mounted to a satellite reception assembly.

13. A method comprising:

in a direct broadcast satellite (DBS) reception assembly:

downconverting and digitizing a received DBS signal, said downconverting and digitizing resulting in a first signal; and

selecting, by a first digital processing circuit, a first plurality of channels of said first signal;

processing, by said first digital processing circuit, one of said selected first plurality of channels to generate a second signal; and

outputting, via a first expansion interface circuit of said first digital processing circuit, said first signal, said selected first plurality of channels, and/or said second signal.

14. The method of claim 13 , comprising:

selecting, by a second digital processing circuit, a second plurality of channels of said first signal;

processing, by said second digital processing circuit, one of said selected second plurality of channels to generate a third signal; and

outputting, via a second expansion interface circuit of said second digital processing circuit, said first signal, said selected second plurality of channels, and/or said third signal.

15. The method of claim 14 , comprising:

transmitting, via a first interface circuit, said second signal in accordance with one or more networking and/or multimedia standards;

transmitting, via a second interface circuit, said third signal in accordance with one or more networking and/or multimedia standards; and

combining, via an aggregation circuit, a signal output by said first interface circuit with a signal output by said second interface circuit to generate a fourth circuit; and

transmit, by said aggregation circuit, said fourth circuit to a client device in accordance with one or more networking and/or multimedia standards.

16. The method of claim 15 , wherein said combining comprises frequency division multiplexing said signal output by said first interface circuit and said signal output by said second interface circuit onto a communication link.

17. The method of claim 14 , wherein processing by said first digital processing circuit comprises demodulating said one of said selected first plurality of channels to recover an MPEG transport stream.

18. The method of claim 17 , wherein said processing by said second digital processing circuit comprises demodulating said one of said selected second plurality of channels to recover an MPEG transport stream.

19. The method of claim 13 , wherein:

said first digital processing circuit is part of a first module residing on a first substrate;

said second digital processing circuit is part of a second module residing on a second substrate; and

said first module and said second module are enclosed in a shared housing.

20. The method of claim 19 , wherein said housing is mounted to a satellite reception assembly.

Assignments (7)