Display device
View Patent ↗Each of a plurality of timing controllers has a synchronization reference signal output terminal from which a synchronization reference signal is output and a synchronization reference signal input terminal to which the synchronization reference signal is input. A master timing controller outputs a predetermined signal of display signals which are input from an external device, from the synchronization reference signal output terminal of the master timing controller as the synchronization reference signal, and the synchronization reference signal is input to the synchronization reference signal input terminals of the master timing controller and a slave timing controller. Accordingly, a luminance difference can be prevented from occurring between divided regions of a display panel due to asynchronization between display signals input to respective timing controllers in a display device in which a plurality of timing controllers are used and the display panel is divided into a plurality of regions.
1. A display device comprising:
a display panel that is divided into a plurality of regions; and
a plurality of timing controllers to which display signals including display data are independently input from an external device for each of the plurality of regions of the display panel and that respectively have synchronization reference signal input terminals to which a synchronization reference signal is input,
wherein the plurality of timing controllers include
a master timing controller that outputs a predetermined signal of the display signals which are input from the external device, from a synchronization reference signal output terminal as the synchronization reference signal;
one or a plurality of slave timing controllers other than the master timing controller, and
wherein the synchronization reference signal input into the synchronization reference signal input terminals of the master timing controller and the slave timing controller.
2. The display device according to claim 1 , wherein each timing controller includes
a memory control unit; and
a driver control signal generation unit,
wherein the memory control unit includes
a write address control section;
a two-port SRAM; and
a read address control section,
wherein the display signals input from the external device include dot clocks,
wherein the write address control section stores the display data input from the external device in the two-port SRAM in synchronization with the dot clocks when the predetermined signal is input, and
wherein the read address control section reads the display data from the two-port SRAM in synchronization with the dot clocks after the synchronization reference signal is input to the synchronization reference signal input terminal and outputs the read display data to the driver control signal generation unit.
3. The display device according to claim 2 , wherein the read address control section reads the display data from the two-port SRAM in synchronization with the dot clocks after a predetermined offset period has elapsed from a time point when the synchronization reference signal is input to the synchronization reference signal input terminal.
4. The display device according to claim 3 , wherein the offset period is set in advance.
5. The display device according to claim 3 , wherein, when N is an integer which is equal to or greater than 1, the offset period corresponds to a cycle of N dot clocks which are input from the external device to the master timing controller.
6. The display device according to claim 5 , wherein a bit width of the two-port SRAM is a bit width of the display data, and wherein the number of words of the two-port SRAM is twice or more the N.
7. The display device according to claim 2 , wherein the read address control section generates an internal display timing signal in synchronization with the reading of the display data from the two-port SRAM and outputs the generated internal display timing signal to the driver control signal generation unit.
8. The display device according to claim 7 , wherein the driver control signal generation unit generates
a display data latch clock;
an output timing clock;
a frame start instruction signal; and
a shift clock.
9. The display device according to claim 8 , wherein the display panel includes
a plurality of drain drivers; and
at least one gate driver,
wherein each of the driver control signal generation units of the plurality of timing controllers outputs the display data, the display data latch clock, and the output timing clock to drain drivers which drive regions corresponding to the self timing controller among the plurality of regions of the display panel, and
wherein the driver control signal generation unit of the master timing controller outputs the frame start instruction signal and the shift clock to at least one gate driver.
10. The display device according to claim 1 , wherein the display signals input from the external device include dot clocks and a horizontal synchronization signal, and
wherein the predetermined signal of the display signals input from the external device is the horizontal synchronization signal.
11. The display device according to claim 1 , wherein the display signals input from the external device include dot clocks and a display timing signal, and
wherein the predetermined signal of the display signals input from the external device is the display timing signal.