Low-volume programmable-output PFC rectifier with dynamic efficiency and transient response optimization
View Patent ↗The present invention is a system, apparatus and method of a PFC rectifier having a programmable output voltage that does not incur a drastic penalty in the overall size or volume of the device, or a significant degradation in efficiency. The PFC rectifier of the present invention may incorporate a two-stage solution for output voltage regulation. The present invention provides a topology of a small-size/volume PFC rectifier with a variable (i.e. programmable) output voltage and a complementary control method. The two-stage system of the present invention incorporates a smaller and lower cost capacitor than the bulky size and costly energy storage capacitors required in conventional prior art. The present invention also achieves tight output regulation. The two-stage topology of the present invention further achieves on-line efficiency optimization and significantly reduces the volume of the downstream stage over the prior art examples through dynamic adjustment of the downstream stage supply voltage.
1. A PFC rectifier with a programmable output voltage operable to reduce the size or volume of a converter in a downstream stage of the PFC rectifier, comprising:
a) a front converter incorporated in a front stage, and said front converter incorporating a non symmetric capacitive divider incorporating a top capacitor and a bottom capacitor, wherein:
i) the top capacitor is operable to store energy at a sufficiently high voltage to provide hold up time and increase a current slew rate during transients to provide a fast dynamic transient response; and
ii) the bottom capacitor is operable to dynamically adjust on-line power processing and regulate the efficiency of a downstream stage of the PFC rectifier; and
b) a buck converter incorporated in the downstream stage.
2. The PFC rectifier of claim 1 , wherein the non symmetric capacitive divider incorporates independently controllable tap voltages, such that the voltages are dynamically controllable.
3. The PFC rectifier of claim 1 , wherein the PFC rectifier incorporates a two-stage system having an on-line efficiency optimization and being operable to dynamically adjust downstream stage supply voltage.
4. The PFC rectifier of claim 1 , wherein the PFC rectifier incorporates a modified flyback design having a single secondary winding, and is operable to perform virtually independent regulation of diver voltages by way of charging one of the following: the bottom capacitor, or the top capacitor and the bottom capacitor.
5. The PFC rectifier of claim 1 , wherein the bottom capacitor is larger than the top capacitor and the top capacitor has a higher voltage.
6. The PFC rectifier of claim 1 , wherein voltage of the bottom capacitor is a centre tap voltage that is adaptively changed to perform on-line power processing efficiency optimization in accordance with conditions in a circuit of the PFC rectifier.
7. The PFC rectifier of claim 1 , wherein the front converter is a flyback converter operable in discontinuous conduction mode.
8. A method for controlling a programmable output voltage in a PFC rectifier that incorporates a converter in a downstream stage having a reduced size and volume, comprising the steps of:
a) providing a non symmetric capacitive divider in a front stage of the PFC rectifier, the divider having a top capacitor and a bottom capacitor;
b) operating the top capacitor to store energy at a sufficiently high voltage to provide hold up time and increase a current slew rate during transients to provide a fast dynamic transient response;
c) operating the bottom capacitor to dynamically adjust on-line power processing and regulate the efficiency of a downstream stage of the PFC rectifier;
d) operating the converter in the downstream stage; and
e) operating a controller to control the front stage and the downstream stage.
9. The method of claim 8 , incorporating the step of performing virtually independent regulation of divider voltages by: charging the bottom capacitor; or charging the top capacitor and the bottom capacitor.
10. The method of claim 8 , incorporating the step of improving transient response of the downstream stage by increasing a voltage applied at the input of the downstream stage to reduce an output capacitor value.
11. The method of claim 8 , incorporating the step of minimizing inductance of the downstream stage by regulating an input voltage introduced to the downstream stage, whereby a centre tap voltage is in the vicinity of an output voltage.
12. The method of claim 8 , incorporating the step of reducing switching losses of the converter by reducing switch voltage of the downstream converter.
13. The method of claim 8 , incorporating the step of the PFC rectifier providing a fast transient response while operating at or virtually at an optimized efficiency point.
14. A PFC rectifier system with a programmable output voltage operable to reduce the size or volume of a converter in the downstream stage of the PFC rectifier, comprising:
a) a flyback-buck two stage converter operable to achieve a combination of a front stage and a downstream stage;
b) an integrated controller operable to regulate the operation of the front stage and the downstream stage;
c) a non symmetric capacitive divider in the front stage, the divider having a top capacitor and a bottom capacitor, wherein:
i) the top capacitor is operable to store energy at a sufficiently high voltage to provide hold up time and increase a current slew rate during transients to provide a fast dynamic transient response; and
ii) the bottom capacitor is operable to dynamically adjust on-line power processing and regulate the efficiency of a downstream stage of the PFC rectifier.
15. The PFC rectifier system of claim 14 , wherein the front stage incorporates a modified flyback converter.
16. The PFC rectifier system of claim 14 , wherein the downstream stage incorporates a conventional buck converter with an extra switch.
17. The PFC rectifier system of claim 14 , wherein voltages of the bottom capacitor and top capacitor are independently regulated.
18. The PFC rectifier system of claim 14 , wherein the controller incorporates two interactive control loops, including:
a) a front-end regulation of the flyback converter operable to achieve virtually a unity factor and to regulate the average values of divider tap voltages based on information provided by an efficiency optimization block; and
b) a downstream regulation of the buck converter operable to achieve tight output voltage regulation and fast dynamic response.
19. The PFC rectifier system of coir 18 , wherein the buck controller applies a minimum deviation control process during transients to recover current in a single on-off switching cycle with minimum output voltage deviation.