IP Library Granted Patent US 8,941,238
Granted Patent B2
US 8,941,238 · App. 13/759,833 · Granted Jan 27, 2015

Semiconductor device

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Quick Facts
Patent No.
US 8,941,238
App. No.
13/759,833
Granted
Jan 27, 2015
Kind
B2
Abstract

A semiconductor device includes a first substrate; a plurality of first electrodes formed on the first substrate; and a first insulating film formed on sidewalls of the plurality of first electrodes. The first insulating film is formed not to fill spaces between the plurality of first electrodes.

Claims (30)

1. A semiconductor device, comprising:

a first substrate;

a plurality of first electrodes formed on the first substrate; and

a first insulating film formed on sidewalls of each of the plurality of first electrodes,

a second substrate;

a plurality of second electrodes formed on the second substrate in positions corresponding to the plurality of first electrodes on the first substrate; and

a second insulating film formed on sidewalls of each of the plurality of second electrodes, wherein

the first insulating film is formed not to fill spaces between adjacent ones of the plurality of first electrodes,

the second insulating film is formed not to fill spaces between adjacent ones of the plurality of second electrodes,

the first substrate and the second substrate are arranged so that the plurality of first electrodes face the corresponding plurality of second electrodes,

the plurality of first electrodes are bonded to the corresponding plurality of second electrodes, and

the first insulating film formed on the sidewalls of each of the plurality of first electrodes is in contact with the second insulating film formed on the sidewalls of each of the plurality of second electrodes.

2. The semiconductor device of claim 1 , wherein each of the plurality of first electrodes and the plurality of second electrodes includes:

a first conductive layer containing a first metal, and

a second conductive layer formed on the first conductive layer, and containing a second metal different from the first metal.

3. The semiconductor device of claim 2 , wherein

the first metal is copper, and

the second metal is tin.

4. The semiconductor device of claim 2 , wherein each of the plurality of first electrodes and the plurality of second electrodes further includes a barrier layer under the first conductive layer.

5. The semiconductor device of claim wherein the barrier layer contains titanium.

6. The semiconductor device of claim 2 , wherein the first conductive layer is a substantially flat plate.

7. The semiconductor device of claim 2 , further comprising: a second conductive layer between the first conductive layer and the substrate, wherein the first insulating film is formed on sidewalls of the second conductive layer.

8. The semiconductor device of claim 7 , wherein the first substrate and the second substrate are substantially flat plates.

9. The semiconductor device of claim 7 , wherein the first conductive layer and the second conductive layer are substantially flat plates.

10. The semiconductor device of claim 1 , wherein the first insulating and the second insulating film are oxide films or organic films.

11. The semiconductor device of claim 1 , wherein the plurality of first electrodes and the plurality of second electrodes contain an alloy containing tin.

12. The semiconductor device of claim 11 , wherein the alloy further contains copper.

13. The semiconductor device of claim 1 , wherein the first substrate and the second substrate are substantially flat plates.

14. The semiconductor device of claim 1 , wherein the first insulating film and the second insulating film are formed of silicon oxide.

15. The semiconductor device of claim 1 , wherein the first insulating film and the second insulating film are formed by chemical vapor deposition.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE ERRONEOUSLY FILED APPLICATION NUMBERS 13/384239, 13/498734, 14/116681 AND 14/301144 PREVIOUSLY RECORDED ON REEL 034194 FRAME 0143. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Dec 24, 2020
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 056788/0362 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 27, 2020
From: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
To: PANASONIC SEMICONDUCTOR SOLUTIONS CO., LTD.
Reel/Frame 052755/0870 →
RELEASE OF SECURITY INTEREST Recorded Mar 4, 2019
From: WILMINGTON TRUST, AS COLLATERAL TRUSTEE
To: TENNECO INC. (F/K/A FEDERAL-MOGUL LLC); FEDERAL-MOGUL MOTORPARTS LLC (F/K/A FEDERAL-MOGUL MOTORPARTS CORPORATION); FEDERAL-MOGUL WORLD WIDE LLC (F/K/A FEDERAL-MOGUL WORLDWIDE, INC.); FEDERAL-MOGUL IGNITION LLC (F/K/A FEDERAL- MOGUL IGNITION COMPANY)
Reel/Frame 048499/0860 →
RELEASE OF SECURITY INTEREST Recorded Mar 4, 2019
From: WILMINGTON TRUST, AS COLLATERAL TRUSTEE
To: TENNECO INC. (F/K/A FEDERAL-MOGUL LLC); FEDERAL-MOGUL MOTORPARTS LLC; FEDERAL-MOGUL WORLD WIDE LLC; FEDERAL-MOGUL IGNITION LLC (F/K/A FEDERAL- MOGUL IGNITION COMPANY)
Reel/Frame 048499/0910 →
RELEASE OF SECURITY INTEREST Recorded Mar 4, 2019
From: WILMINGTON TRUST, AS COLLATERAL TRUSTEE
To: TENNECO INC.; FEDERAL-MOGUL MOTORPARTS LLC; FEDERAL-MOGUL WORLD WIDE LLC; FEDERAL-MOGUL IGNITION LLC
Reel/Frame 048499/0973 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 10, 2014
From: PANASONIC CORPORATION
To: PANASONIC INTELLECTUAL PROPERTY MANAGEMENT CO., LTD.
Reel/Frame 034194/0143 →