IP Library Granted Patent US 9,418,247
Granted Patent B2
US 9,418,247 · App. 13/762,237 · Granted Aug 16, 2016

Security system and methods for integrated devices

Inventors: Sanjay Bhandari (San Jose, CA); Tony Maraldo (San Jose, CA)
Assignee: MCUBE INC.
G06F21/73
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Quick Facts
Patent No.
US 9,418,247
App. No.
13/762,237
Granted
Aug 16, 2016
Kind
B2
Abstract

Systems and methods for implementing security mechanisms in integrated devices and related structures. This method can include validating a device ID, generating a random value based on selected seed parameters, performing logic operations from hardware using the random value, and validating the integrated device based on logic operations from software using the random value. The system can include executable instructions for performing the method in a computing system. Various embodiments of the present invention represent several implementations of a security mechanism for integrated devices. These implementations provide several levels of encryption or protection of integrated devices, which can be tailored depending on the hardware and/or software requirements of specific applications.

Claims (35)

1. A method for implementing a security mechanism in an integrated MEMS (Micro-Electro-Mechanical-Systems) device including, the integrated MEMS device configured with a MEMS sensor, a MEMS test module, and an internal pattern generator, the integrated MEMS device being further configured with an output register associated with a corresponding sensing operation, wherein, in a test mode, the output register is configured to receive a value from the internal pattern generator or internal logic, the integrated MEMS device being electrically coupled to a computing system programmed to perform the method, the method comprising:

reading, by a processor disposed within the computing system, a device ID from a device ID register disposed within the integrated MEMS device;

determining, by the processor, whether the device ID of the integrated MEMS device is valid;

determining, by the processor, a random value, wherein determining the random value includes enabling, by the MEMS test module a MEMS process to determine the random value or by setting a value associated with a duty cycle of the internal pattern generator in the output register and then reading from the output register to obtain the value from the internal pattern generator;

writing, by the processor, the random value to a security register disposed within the integrated device;

determining, by the processor, a configuration value;

writing, by the processor, the configuration value to a security configuration register disposed within the integrated device;

determining, by a logic module disposed within the integrated device, an operation result via a logic operation using the random value and the configuration value;

writing the operation result to the security register;

determining, by the processor, a validation result using the logic operation;

reading, by the processor, the operation result from the security register; and

determining, by the processor, whether the integrated MEMS device is valid using the device ID, the validation result, and the operation result.

2. The method of claim 1 wherein the security configuration register comprises the device ID register.

3. The method of claim 2 wherein the logic module comprises a XOR logic module coupled to the security register and the logic operation comprises an XOR operation.

4. The method of claim 1 wherein the logic module comprises a linear feedback shift register (LFSR) module coupled to the security register.

5. The method of claim 4 wherein the logic operation comprises a linear feedback shift register (LSFR) operation, the LFSR operation being performed k times where k is an integer greater than or equal to 1; and

wherein reading the operation result from the security register comprises reading the operation result from the security register after waiting k clock cycles.

6. The method of claim 4 wherein the configuration value comprises a polynomial.

7. A computing system for processing data from an integrated MEMS (Micro-Electro-Mechanical-Systems) device electrically coupled to the computing system, the system comprising:

the integrated MEMS device including a MEMS sensor, a MEMS test module, an internal pattern generator, a logic module, a device ID register, a security register, a security configuration register, and an output register associated with a sensing operation, wherein, in a test mode, the output register receives a respective value from the internal pattern generator;

a tangible memory for storing a plurality of executable instructions;

a processor coupled to the tangible memory and the integrated MEMS device, wherein the processor is programmed to perform a plurality of functions by the plurality of executable instructions;

wherein the plurality of executable instructions comprise:

executable code that programs the processor to read a device ID from the device ID register;

executable code that programs the processor to determine whether the device ID of the integrated MEMS device is valid;

executable code that programs the processor to determine a random value, wherein the code that programs the processor to determine the random value includes

executable code that enables, by the MEMS test module a MEMS test process to determine the random value by setting a value associated with a duty cycle of the internal pattern generator in the output register, and then reading from the output register to obtain the value from the internal pattern generator;

executable code that programs the processor to write the random value to the security register;

executable code that programs the processor to determine a configuration value;

executable code that programs the processor to write the configuration value to the security configuration register;

executable code that programs the logic module to determine an operation result via a logic operation using the random value and the configuration value;

executable code that programs the processor to write the operation result to the security register;

executable code that programs the processor to determine a validation result using the logic operation;

executable code that programs the processor to read the operation result from the security register; and

executable code that programs the processor to determine whether the integrated MEMS device is valid using the device ID, the validation result, and the operation result.

Assignments (10)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 8, 2026
From: MOVELLA INC.
To: PACIFIC RESEARCH GROUP PTE. LTD.
Reel/Frame 075352/0224 →
NOTICE OF GRANT OF SECURITY INTEREST IN PATENTS Recorded Nov 15, 2022
From: MOVELLA INC.
To: WILMINGTON SAVINGS FUND SOCIETY, FSB, AS AGENT
Reel/Frame 061948/0764 →
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2022
From: EASTWARD FUND MANAGEMENT, LLC
To: MOVELLA INC. (FORMERLY KNOWN AS MCUBE, INC.)
Reel/Frame 061940/0635 →
RELEASE OF SECURITY INTEREST Recorded Nov 15, 2022
From: EASTWARD FUND MANAGEMENT, LLC
To: MOVELLA INC.
Reel/Frame 061940/0602 →
RELEASE OF SECURITY INTEREST Recorded Nov 14, 2022
From: SILICON VALLEY BANK
To: MOVELLA INC. (FORMERLY KNOWN AS MCUBE, INC.)
Reel/Frame 061936/0024 →
CHANGE OF NAME Recorded Oct 31, 2022
From: MCUBE, INC
To: MOVELLA INC.
Reel/Frame 061600/0985 →
SECURITY INTEREST Recorded Dec 16, 2021
From: MOVELLA INC.
To: EASTWARD FUND MANAGEMENT, LLC
Reel/Frame 058520/0690 →
SECURITY INTEREST Recorded Sep 2, 2020
From: MCUBE, INC.
To: EASTWARD FUND MANAGEMENT, LLC
Reel/Frame 053826/0626 →
SECURITY INTEREST Recorded Jun 11, 2020
From: MCUBE, INC.
To: SILICON VALLEY BANK
Reel/Frame 052909/0119 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 23, 2013
From: BHANDARI, SANJAY; MARALDO, ANTHONY
To: MCUBE INC.
Reel/Frame 030478/0211 →
Continuity (2)
Provisional Application 61596192 · Feb 7, 2012
Related Publication 20130219526A1 · Aug 22, 2013