Finite state machine for system management

1. A programmable finite state machine configured to transition from a current state to a next state after receiving an input symbol, the input symbol comprising a plurality of inputs, the next state and the current state being represented by N bits and the input symbol being represented by I bits, the finite state machine being further configured to generate an output symbol comprising a plurality of outputs, the output symbol being represented by W bits, the output symbol being dependent on the current state, the finite state machine comprising:

a register configured to store the current state;

a first look-up table configured to store a plurality of output symbols indexed by address and to provide at an output a first output symbol addressed by the value of the register; and

a microcode table with a plurality of entries, wherein each entry of the plurality of entries represents a state transition of a number of state transitions of the programmable finite state machine and includes microcode logic for evaluating the state transition simultaneously with other state transitions of other entries of the plurality of entries, wherein the microcode logic includes:

a plurality of programmable fields;

a comparator for comparing the current state to a first programmable field of the plurality of programmable fields;

a multiplexer circuit for evaluating a portion of the input symbol against second and third programmable fields of the plurality of programmable fields; and

an AND-gate circuit configured to receive an output of the comparator and an output of the multiplexer circuit and, if evaluated as true, to pass a value of a fourth programmable field of the plurality of programmable fields to the register.

2. The programmable finite state machine according to claim 1 , wherein the microcode table is configured to concurrently compare all entries for transitioning according to the current state and wherein the second and third programmable fields are configured to store a transition Boolean function for transitioning from the current state to the next state by processing the input symbol.

3. The programmable finite state machine according to claim 1 , wherein fixed sections of the microcode table are assigned to each of the states from which the finite state machine is to be transitioned and wherein the current state selects the microcode section to be considered for processing.

4. The programmable finite state machine according to claim wherein the microcode is content addressable memory, and

wherein the first programmable field is a state information field, the state information field being further configured to store a state from which the finite state machine is to be transitioned in a from-state-field, and the microcode table being further configured to select all entries for processing where the from-state-field matches the current state.

5. The programmable finite state machine according to claim 2 , wherein the transition condition field is divided into a select field configured to store a select symbol represented by S bits and a function field configured to store a function symbol represented by V bits, the microcode table is configured to select a number of inputs out of the input symbol as a function of the select symbol, and the microcode table is further configured to process a transition Boolean function represented by the function symbol on the selected inputs.

6. The programmable finite state machine according to claim 5 , wherein the transition Boolean function is implemented as a second lookup table with the selected inputs being the address of the second lookup table.

7. The programmable finite state machine according to claim 1 , wherein individual entries of the microcode table are implemented as ROM and/or combinational logic.

8. The programmable finite state machine according to claim 1 , wherein a set of states and transitions is divided into a plurality of disjunct subsets, each subset being assigned to a specific mode; and wherein the finite state machine is reprogrammed to the disjunct subset according to the specific mode.

9. The programmable finite state machine according to claim 8 , wherein one mode and corresponding subset relates to a sleep mode of a system and/or wherein one mode and corresponding subset relates to a normal processing mode of system.

10. A system-on-a-chip comprising a programmable finite state machine according to claim 1 , wherein the finite state machine is configured to provide a system management functionality, the system management functionality being configured to manage a plurality of components on a chip.

11. The system according to claim 10 , wherein the state of the finite state machine comprises sleep and/or high speed processing and/or slow speed processing; and/or wherein the inputs of the finite state machine comprise power requests and/or clock requests; and/or wherein the output of the finite state machine comprises voltage controls and/or clock.