Non-volatile memory system with reset control mechanism and method of operation thereof
View Patent ↗A method of operation of a non-volatile memory system includes: providing a control field effect transistor having a source electrode and a body-tie electrode; coupling a resistive storage element to the source electrode; and opening a well switch coupled to the body-tie electrode for increasing a well voltage and resetting the resistive storage element by the source electrode floating on the well voltage.
1. A non-volatile memory system comprising:
a control field effect transistor having a source electrode and a body-tie electrode;
a resistive storage element coupled to the source electrode; and
a well switch, coupled to the body-tie electrode, opened for increasing a well voltage and the resistive storage element reset with the source electrode elevated by the well voltage.
2. The system as claimed in claim 1 wherein the resistive storage element reset includes a low resistance state transitioned to a high resistance state.
3. The system as claimed in claim 1 further comprising:
a first electrode, of the resistive storage element, coupled to the source electrode; and
a second electrode, of the resistive storage element, coupled to a plate voltage for establishing a voltage reference for the resistive storage element.
4. The system as claimed in claim 1 further comprising:
a drain electrode, of the control field effect transistor, coupled to a bit line; and
a gate electrode, of the control field effect transistor, coupled to a word line for addressing the resistive storage element.
5. The system as claimed in claim 1 further comprising a control block for coordinating the opening of the well switch for resetting the resistive storage element.
6. The system as claimed in claim 1 further comprising:
a conductive layer in direct contact with a transformation layer in the resistive storage element; and
a conductive thread formed in the transformation layer dissociated by the reset of the resistive storage element.
7. The system as claimed in claim 6 wherein the resistive storage element reset includes a low resistance state transitioned to a high resistance state and the conductive thread dissociated back into the conductive layer.
8. The system as claimed in claim 6 further comprising:
a first electrode, of the resistive storage element, coupled to the source electrode; and
a second electrode, of the resistive storage element, coupled to a plate voltage for establishing a voltage reference for the resistive storage element includes the conductive thread formed or dissociated.
9. The system as claimed in claim 6 further comprising:
a drain electrode, of the control field effect transistor, coupled to a bit line includes a control block for signaling on the bit line; and
a gate electrode, of the control field effect transistor, coupled to a word line for addressing the resistive storage element includes an address driver coupled to the word line for signaling on the word line.
10. The system as claimed in claim 6 further comprising a control block for coordinating the opening of the well switch for resetting the resistive storage element includes the well voltage increased by charge accumulation.