Malware and tamper resistant computer architecture
View Patent ↗Generally described herein are methods and systems for enhanced tamper and malware resistant computer architectures. A system for enhanced tamper and malware resistance can include a harvardizer configured to receive comingled instructions and data and produce separated instructions and data. A data memory can be configured to receive the separated data. An instruction memory that is physically separate from the data memory can be configured to receive the separated instructions. The system can include one or more computer processors that can be configured to execute the separated instructions and data. The system can include one or more encryptors or decryptors to help thwart injection based attacks.
1. A computer system comprising:
a harvardizer configured to receive comingled instructions and data and produce separated instructions and data;
a first encryptor connected to the harvardizer to receive the separated data and generate encrypted data;
a data memory connected to the first encryptor configured to receive the encrypted data;
a first decryptor connected to the data memory to decrypt the encrypted data;
a second encryptor connected to the harvardizer to receive the separated instructions and generate encrypted instructions;
an instruction memory physically separate from the data memory connected to the second encryptor, the instruction memory configured to receive the encrypted instructions;
a second decryptor connected to the instruction memory to decrypt the encrypted instructions; and
one or more processors connected to the first and second decryptors and configured to process the separated instructions and data, the one or more processors including a first transformation execution engine to process sixteen-bit decrypted data and decrypted instructions, a second transformation execution engine to execute thirty-two bit decrypted data and decrypted instructions, and a third transformation execution engine to execute sixty-four bit decrypted data and decrypted instructions,
wherein the data memory and the instruction memory are configured in a pure Harvard architecture format.
2. The computer system of claim 1 , wherein the one or more processors includes one or more transformation execution engines configured to execute legacy Von Neumann code configured in a Harvard format.
3. The computer system of claim 2 , wherein the one or more transformation execution engines include a fourth transformation execution engine configured to eight bit instructions and data.
4. A method comprising:
receiving, at a computer, instructions and data in a Von Neumann format;
converting the instructions and data to a Harvard format by separating the comingled instructions and data;
encrypting the separated instructions and storing the encrypted instructions in an instruction memory;
encrypting the separated data and storing the encrypted data in a data memory, wherein the instruction memory and the data memory are configured in a pure Harvard architecture format;
decrypting the encrypted data and sending the decrypted data to a transformation execution engine of a plurality of transformation execution engines;
decrypting the encrypted instruction and sending the decrypted instructions to the transformation execution engine, the plurality of transformation execution engines including a first transformation execution engine to process sixteen-bit decrypted data and decrypted instructions, a second transformation execution engine to execute thirty-two bit decrypted data, and a third transformation execution engine to execute sixty-four bit decrypted data; and
processing, using the transformation execution engine, the decrypted data and instructions.