IP Library Patent Application 13767191
Patent Application
App. No. 13/767,191

METHODS AND APPARATUS FOR SYNCHRONIZING MULTIPLE PROCESSORS OF A VIRTUAL MACHINE

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Quick Facts
Patent No.
US None
App. No.
13/767,191
Abstract

Methods and apparatus for synchronizing multiple virtual processors of a virtual machine are disclosed. A hypervisor schedules a first virtual processor in a virtual machine to execute using a first physical processor. Subsequently, the hypervisor receives an indication from the first virtual processor that it is waiting on a second different virtual processor. If the second virtual processor is not already running on another physical processor, the hypervisor saves the priority associated with the first virtual processor, lowers the priority associated with the first virtual processor, and schedules the second virtual processor to execute using the first physical processor or another physical processor.

Claims (73)

1 . A method of synchronizing multiple virtual processors of a virtual machine, the method comprising:

scheduling a first virtual processor in the virtual machine to execute using a first physical processor;

receiving an indication from the first virtual processor that the first virtual processor is waiting on a second different virtual processor in the virtual machine;

determining if the second virtual processor is already executing using a second different physical processor;

lowering a priority associated with the first virtual processor if the second virtual processor is not already executing using the second different physical processor; and

scheduling the second virtual processor to execute using at least one of the first physical processor, the second physical processor, and a third physical processor.

2 . The method of claim 1 , wherein the priority associated with the first virtual processor remains the same if the second virtual processor is already executing using the second physical processor.

3 . The method of claim 1 , wherein the first virtual processor and second virtual processor are both scheduled to execute if the second virtual processor is already executing using the second physical processor.

4 . The method of claim 1 , wherein receiving the indication from the first virtual processor that the first virtual processor is waiting on the second virtual processor includes receiving an identifier indicative of the second virtual processor.

5 . The method of claim 1 , further comprising saving a current priority associated with the first virtual processor before lowering the priority associated with the first virtual processor, and subsequently raising the priority associated with the first virtual processor back to the saved priority in response to receiving an indication from the second virtual processor.

6 . The method of claim 5 , wherein the indication from the second virtual processor includes at least one of (1) an indication that the second virtual processor has completed an operation and (2) an indication that the second virtual processor has released a resource such that the first virtual processor is longer waiting on the second virtual processor.

7 . The method of claim 1 , wherein the first virtual processor is associated with a base priority.

8 . The method of claim 7 , further comprising receiving an interrupt associated with the first virtual processor and raising the priority associated with the first virtual processor to the base priority in response to receiving the interrupt.

9 . The method of claim 1 , wherein lowering the priority associated with the first virtual processor includes lowering the priority associated with the first virtual processor to a lowest priority.

10 . The method of claim 1 , wherein scheduling the first virtual processor and the second virtual processor is performed by a hypervisor.

11 . An apparatus for synchronizing multiple virtual processors of a virtual machine, the apparatus comprising:

a hypervisor; and

a first physical processor operatively coupled to the hypervisor, wherein the hypervisor is structured to:

schedule a first virtual processor in the virtual machine to execute using the first physical processor;

receive an indication from the first virtual processor that the first virtual processor is waiting on a second different virtual processor in the virtual machine;

determine if the second virtual processor is already executing using a second different physical processor;

lower a priority associated with the first virtual processor if the second virtual processor is not already executing using the second different physical processor; and

schedule the second virtual processor to execute using at least one of the first physical processor, the second physical processor, and a third physical processor.

12 . The apparatus of claim 11 , further comprising the second physical processor, wherein the second physical processor is operatively coupled to the hypervisor.

13 . The apparatus of claim 11 , wherein the hypervisor comprises software executing at least in part on the first physical processor.

14 . The apparatus of claim 11 , wherein the hypervisor is structured to maintain the priority associated with the first virtual processor if the second virtual processor is already executing using the second physical processor.

15 . The apparatus of claim 11 , wherein the first virtual processor and second virtual processor are both scheduled to execute if the second virtual processor is already executing using the second physical processor.

16 . The apparatus of claim 11 , wherein the hypervisor is structured to receive the indication from the first virtual processor that the first virtual processor is waiting on the second virtual processor includes being structured to receive an identifier indicative of the second virtual processor.

17 . The apparatus of claim 11 , wherein the hypervisor is structured to save a current priority associated with the first virtual processor before lowering the priority associated with the first virtual processor, and subsequently raise the priority associated with the first virtual processor back to the saved priority in response to receiving an indication from the second virtual processor.

18 . The apparatus of claim 17 , wherein the indication from the second virtual processor includes at least one of (1) an indication that the second virtual processor has completed an operation and (2) an indication that the second virtual processor has released a resource such that the first virtual processor is longer waiting on the second virtual processor.

19 . The apparatus of claim 11 , wherein the first virtual processor is associated with a base priority.

20 . The method of claim 19 , wherein the hypervisor is structured to receive an interrupt associated with the first virtual processor and raise the priority associated with the first virtual processor to the base priority in response to receiving the interrupt.

21 . The apparatus of claim 11 , wherein the hypervisor being structured to lower the priority associated with the first virtual processor includes being structured to lower the priority associated with the first virtual processor to a lowest priority.

22 . A computer readable memory storing instructions structured to cause an electronic device to:

schedule a first virtual processor in the virtual machine to execute using a first physical processor;

receive an indication from the first virtual processor that the first virtual processor is waiting on a second different virtual processor in the virtual machine;

determine if the second virtual processor is already executing using a second different physical processor;

lower a priority associated with the first virtual processor if the second virtual processor is not already executing using the second different physical processor; and

schedule the second virtual processor to execute using at least one of the first physical processor, the second physical processor, and a third physical processor.

23 . The computer readable memory of claim 22 , wherein the instructions are structured to cause the electronic device to maintain the priority associated with the first virtual processor if the second virtual processor is already executing using the second physical processor.

24 . The computer readable memory of claim 22 , wherein the instructions are structured to cause the electronic device to schedule the first virtual processor and second virtual processor to execute if the second virtual processor is already executing using the second physical processor.

25 . The computer readable memory of claim 22 , wherein the instructions being structured to receive the indication from the first virtual processor that the first virtual processor is waiting on the second virtual processor includes being structured to receive an identifier indicative of the second virtual processor.

26 . The computer readable memory of claim 22 , wherein the instructions are structured to cause the electronic device to save a current priority associated with the first virtual processor before lowering the priority associated with the first virtual processor, and subsequently raise the priority associated with the first virtual processor back to the saved priority in response to receiving an indication from the second virtual processor.

27 . The method of claim 26 , wherein the indication from the second virtual processor includes at least one of (1) an indication that the second virtual processor has completed an operation and (2) an indication that the second virtual processor has released a resource such that the first virtual processor is longer waiting on the second virtual processor.

28 . The computer readable memory of claim 22 , wherein the first virtual processor is associated with a base priority.

29 . The computer readable memory of claim 28 , wherein the instructions are structured cause the electronic device to receive an interrupt associated with the first virtual processor and raise the priority associated with the first virtual processor to the base priority in response to receiving the interrupt.

30 . The computer readable memory of claim 22 , wherein the instructions being structured to cause the electronic device to lower the priority associated with the first virtual processor includes being structured to lower the priority associated with the first virtual processor to a lowest priority.

31 . A method of synchronizing multiple virtual processors of a virtual machine, the method comprising:

scheduling a first virtual processor in the virtual machine to execute using at least one physical processor;

receiving an indication from the first virtual processor that the first virtual processor is waiting for a resource from a second virtual processor;

saving a priority level of the first virtual processor;

lowering the priority level of the first virtual processor; and

scheduling the second virtual processor to execute using the at least one physical processor.

32 . The method of claim 31 , further comprising:

receiving an indication from the second virtual processor that the second virtual processor has released the resource; and

restoring the priority level of the first virtual processor to the saved priority level.

33 . The method of claim 31 , wherein the priority level of the first virtual processor remains the same if the second virtual processor is already executing.

34 . The method of claim 31 , wherein receiving the indication from the first virtual processor that the first virtual processor is waiting for a resource held by the second virtual processor includes receiving an identifier indicative of the second virtual processor.

35 . The method of claim 31 , further comprising:

receiving an interrupt associated with the first virtual processor; and

raising the priority level associated with the first virtual processor to a base priority in response to receiving the interrupt associated with the first virtual processor.

36 . The method of claim 31 , wherein lowering the priority level associated with the first virtual processor includes lowering the priority level associated with the first virtual processor to a lowest priority.

37 . The method of claim 31 , wherein scheduling the first virtual processor and the second virtual processor is performed by a hypervisor.

38 . The method of claim 31 , further comprising:

receiving an indication from a third virtual processor that the third virtual processor is waiting for the resource from the second virtual processor;

saving a priority level of the third virtual processor; and

lowering the priority level of the third virtual processor.

39 . The method of claim 38 , further comprising:

receiving an indication from the second virtual processor that the second virtual processor has released the resource; and

restoring the priority level of the third virtual processor to the saved priority level.

40 . The method of claim 38 , further comprising:

receiving an interrupt associated with the third virtual processor; and

raising the priority level associated with the third virtual processor in response to receiving the interrupt associated with the third virtual processor.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2014
From: OPEN KERNEL LABS, INC.
To: GENERAL DYNAMICS C4 SYSTEMS, INC.
Reel/Frame 032985/0455 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 15, 2014
From: VAN SCHAIK, CARL FRANS
To: GENERAL DYNAMICS C4 SYSTEMS, INC.
Reel/Frame 031975/0480 →