Multi-reference clock synchronization techniques
View Patent ↗Efficient synchronization techniques that support multiple reference clocks in an EQAM device. Consider a plurality of different modulators in the EQAM device receiving data from a corresponding plurality of different sources having corresponding different timing references (i.e., different source reference clocks). To accommodate this, the modulators all operate using a common system clock, and each modulator is provided with a phase synchronizer. The phase synchronizer synchronizes the modulated symbol phases to the corresponding reference clock.
1. An apparatus, comprising:
a phase synchronizer configured to generate symbol phase information based on a reference clock and a system clock; and
a modulator coupled to the phase synchronizer, the modulator being configured to generate a symbol stream based on received data and the symbol phase information.
2. The apparatus of claim 1 , wherein the modulator is further configured to synchronize with the reference clock based on the symbol phase information.
3. The apparatus of claim 2 , wherein the modulator is further configured to operate in response to the system clock.
4. The apparatus of claim 1 , wherein the phase synchronizer is configured to operate in response to the system clock.
5. The apparatus of claim 1 , wherein the system clock is independent of the reference clock.
6. The apparatus of claim 1 , wherein the received data is received from a data source, the data source being associated with the reference clock.
7. The apparatus of claim 1 , wherein the phase synchronizer comprises:
a phase accumulator configured to generate the symbol phase information based on phase adjustment information;
a phase-locked loop (PLL) configured to generate the phase adjustment information based on received phase information; and
an edge detector configured to detect an edge of the reference clock, determine a difference between the detected edge of the reference clock and an edge of the system clock, and generate the phase information based on the determined difference.
8. The apparatus of claim 7 , wherein the phase accumulator, the PLL, and the edge detector are configured to operate in response to the system clock.
9. The apparatus of claim 1 , wherein the phase synchronizer comprises:
an edge detector configured to detect an edge of the reference clock, determine a difference between the detected edge of the reference clock and an edge of the system clock, and generate phase information based on the determined difference;
a phase-locked loop (PLL) configured to generate phase adjustment information based on the phase information and a feedback signal;
a symbol clock generator configured to generate a symbol phase signal based on the phase adjustment information; and
a phase accumulator configured to generate the feedback signal based on the symbol phase signal.
10. The apparatus of claim 9 , wherein the symbol clock generator is further configured to generate a symbol clock signal based on the phase adjustment information and provide the symbol clock signal to the modulator.
11. The apparatus of claim 9 , wherein the edge detector, the PLL, the symbol clock generator, and the phase accumulator are configured to operate in response to the system clock.
12. A method, comprising:
receiving a reference clock and a system clock;
generating symbol phase information based on the reference clock, and the system clock;
receiving data from a data source;
generating, by a modulator, a symbol stream based on the received data and the symbol phase information; and
synchronizing the modulator with the reference clock based on the symbol phase information.
13. The method of claim 12 , wherein the generating the symbol stream comprises generating the symbol stream based on the system clock.
14. The method of claim 12 , wherein the system clock is independent of the reference clock.
15. The method of claim 12 , wherein the data source is associated with the reference clock.
16. The method of claim 12 , wherein the generating the symbol phase information comprises:
detecting an edge of the reference clock;
determining a difference between the detected edge of the reference clock and an edge of the system clock;
generating phase information based on the determined difference;
generating phase adjustment information based on the phase information; and
generating the symbol phase information based on the phase adjustment information.
17. The method of claim 12 , wherein the generating the symbol phase information comprises:
detecting an edge of the reference clock;
determining a difference between the detected edge of the reference clock and an edge of the system clock;
generating phase information based on the determined difference;
generating phase adjustment information based on the phase information and a feedback signal;
generating a symbol phase signal based on the phase adjustment information; and
generating the feedback signal based on the symbol phase signal.
18. The method of claim 17 , further comprising:
generating a symbol clock signal based on the phase adjustment information; and
providing the symbol clock signal to the modulator.
19. An apparatus, comprising:
a phase synchronizer configured to generate symbol phase information based on a reference clock and a system clock, the reference clock being independent of the system dock; and
a modulator coupled to the phase synchronizer, the modulator being configured to generate a symbol stream based on received data and the symbol phase information, and synchronize with the reference clock based on the symbol phase information.
20. The apparatus of claim 19 , further comprising:
a symbol clock generator, the modulator being coupled to the phase synchronizer via the symbol clock generator, wherein the symbol clock generator is configured to generate a symbol clock signal and provide the symbol clock signal to the modulator.