Ethernet UDP checksum compensation
In the methods and devices of the present disclosure, a dummy compensation word is added to the data packet such that the UDP checksum value need not be modified from any previous value, regardless of changes to the UDP payload. Because the UDP checksum value is not modified in embodiments of the present disclosure, there is no delay waiting for a UDP checksum value to be calculated and no need for additional buffers to store the data packet contents because of UDP checksum calculations. The dummy compensation word is calculated so that the unmodified value maintained in the checksum is the checksum for the data packet including the dummy compensation word. By placing the compensation word in the data packet after the last word in the UDP payload, there is no, or very minimal, processing delay and data packet buffering hardware is significantly reduced.
1. A method for checksum calculation of a data packet comprising a plurality of digital information units including a checksum and a payload, the method comprising:
(a) reading the packet unit by unit, including reading the checksum;
(b) accumulating the units being read in (a) to a running sum according to a checksum calculation formula for the data packet;
(c) calculating a compensation value from the running sum of (b) such that including the compensation value in the running sum validates the checksum read in (a);
(d) adding an extra digital information unit in the data packet near an end of the payload; and
(e) storing a compensation value in the extra digital information unit.
2. The method according to claim 1 wherein (d) further comprises incrementing a length datum in the data packet by one digital information unit prior to (b) accumulating the length datum.
3. The method according to claim 1 wherein (d) further comprises post-pending the extra digital information unit to the payload.
4. The method according to claim 3 further comprising transmitting the data packet unit-by-unit in real-time.
5. The method according to claim 1 wherein (b) further comprises accumulating the running sum in a register having a most significant digital information unit and a least significant digital information unit.
6. The method according to claim 5 wherein (c) further comprises calculating the compensation value equivalent to the formula ˜(MS+LS−1)+˜checksum where MS is the most significant digital information unit, LS is the least significant digital information unit and ˜ is a bit inversion operator.
7. The method according to claim 1 wherein the checksum calculation formula is selected from the group comprising a UDP packet checksum formula and an FRP packet checksum formula.
8. A device for checksum calculation of a data packet comprising a plurality of digital information units including a checksum and a payload, the device comprising:
circuitry (a) for reading the packet unit by unit, including reading the checksum;
circuitry (b) for accumulating the units being read by circuitry (a) to a running sum according to a checksum calculation formula for the data packet;
circuitry (c) for calculating a compensation value from the running sum such that including the compensation value in the running sum validates the checksum read in circuitry (a);
circuitry (d) for adding an extra digital information unit in the data packet near an end of the payload; and
circuitry (e) for storing a dummy value in the extra digital information unit.
9. The device according to claim 8 wherein circuitry (d) comprises circuitry for incrementing a length datum in the data packet by one digital information unit prior to circuitry (b) accumulating the length datum.
10. The device according to claim 8 wherein circuitry (d) comprises circuitry for post-pending the extra digital information unit to the payload.
11. The device according to claim 10 further comprising circuitry for transmitting the data packet unit-by-unit in real-time.
12. The device according to claim 8 wherein circuitry (b) comprises circuitry for accumulating the running sum in a register having a most significant digital information unit and a least significant digital information unit.
13. The device according to claim 12 wherein circuitry (c) comprises circuitry for calculating the compensation value equivalent to the formula ˜(MS+LS−1)+˜checksum where MS is the most significant digital information unit, LS is the least significant digital information unit and ˜ is a bit inversion operator.
14. The device according to claim 8 wherein the checksum calculation formula is selected from the group comprising a UDP packet checksum formula and an FRP packet checksum formula.
15. A device for checksum calculation of a data packet comprising a plurality of digital information units including a checksum and a payload, the device comprising:
a processor for executing instructions stored in a non-transitory memory;
the instructions comprising:
instructions (a) for reading the packet unit by unit, including reading the checksum;
instructions (b) for accumulating the units being read in instructions (a) to a running sum according to a checksum calculation formula for the data packet;
instructions (c) for calculating a compensation value from the running sum of instructions (b) such that including the compensation value in the running sum validates the checksum read in instructions (a);
instructions (d) for adding an extra digital information unit in the data packet near an end of the payload; and
instructions (e) for storing a dummy value in the extra digital information unit.
16. The device according to claim 15 wherein instructions (d) further comprises incrementing a length datum in the data packet by one digital information unit prior to instructions (b) accumulating the length datum.
17. The device according to claim 15 wherein instructions (d) further comprises post-pending the extra digital information unit to the payload.
18. The device according to claim 17 further comprising transmitting the data packet unit-by-unit in real-time.
19. The device according to claim 15 wherein instructions (b) further comprises accumulating the running sum in a register having a most significant digital information unit and a least significant digital information unit.
20. The device according to claim 19 wherein instructions (c) further comprises calculating the compensation value equivalent to the formula ˜(MS+LS−1)+˜checksum where MS is the most significant digital information unit, LS is the least significant digital information unit and ˜ is a bit inversion operator.