IP Library Granted Patent US 9,300,352
Granted Patent B2
US 9,300,352 · App. 13/769,727 · Granted Mar 29, 2016

Transceiver with board-level configuration of on-chip or external transmit/receive switch

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Quick Facts
Patent No.
US 9,300,352
App. No.
13/769,727
Granted
Mar 29, 2016
Kind
B2
Abstract

A transceiver includes an integrated circuit that enables board-level configuration of an on-chip or external transmit/receive switch. The transceiver uses a high-Q matching network, at least part of which is external, that improves receiver performance; increases transmit power while allowing for configuration of the same chip to use an internal TR switch, or external TR switch by changing connection at the board level rather than the chip level.

Claims (29)

1. A wireless communications transceiver, comprising:

a transceiver integrated circuit comprising a transmitter with transmitter signal path and a receiver with receiver signal path;

an antenna, external to the transceiver integrated circuit, selectively connected in a transmission mode to the transmitter signal path and in reception mode to the receiver signal path, the antenna selectively connected, in the transmission mode, to the transmitter signal path by a series switch (ON) located within the transceiver integrated circuit in the transmitter signal path and isolated from the receiver signal path by at least a switched (ON) parallel resonant circuit that presents a high impedance load to the transmitter, and in the reception mode, both the series switch and the switch for the parallel resonant circuit are (OFF) to prevent signal loss, the series switch including electrostatic discharge (ESD) protection circuitry comprising a plurality of diodes connected between a gate and drain, and gate and source, of the series switch; and

a high-Q matching network, comprising one or more elements external to the transceiver integrated circuit and connected between the antenna and the receiver signal path, the one or more elements comprising at least an external LNA input inductor resonating with a capacitance of the parallel resonant circuit at a transmission frequency of interest so that minimal transmit power is dissipated in the receiver signal path.

2. A wireless communications transceiver, as per claim 1 , wherein the receiver signal path further comprises an LNA and the high-Q matching network connects to an input of the LNA through an input port of the transceiver integrated circuit.

3. A wireless communications transceiver, as per claim 2 , wherein the external LNA input inductor of the high-Q matching network comprises an external high-Q discrete inductor.

4. A wireless communications transceiver, as per claim 1 , wherein the antenna, external to the transceiver integrated circuit, is selectively connected to the transmitter or receiver signal path by an external transmit/receive (TR) switch.

5. A wireless communications transceiver, as per claim 1 , wherein the plurality of diodes are placed in one or more deep-n wells.

6. A wireless communications transceiver, as per claim 1 , wherein the transmitter signal path further comprises at least a power amplifier (PA) connected to an output of the transmitter.

7. A wireless communications transceiver, as per claim 1 , wherein the high-Q matching network comprises a resonating capacitor coupled to the external LNA input inductor.

8. A wireless communications transceiver, as per claim 1 , wherein the transceiver is part of an RF transceiver, user equipment (UE) transceiver, base station (BS) transceiver, wireless transceiver, LTE transceiver or MIMO transceiver.

9. A system comprising a communications transceiver, comprising:

a transceiver integrated circuit comprising a transmitter with transmitter signal path and a receiver with receiver signal path;

an antenna, external to the transceiver integrated circuit, selectively connected in a transmission mode to the transmitter signal path and in reception mode to the receiver signal path, the antenna selectively connected, in the transmission mode, to the transmitter signal path by a series switch (ON) located within the transceiver integrated circuit in the transmitter signal path and isolated from the receiver signal path by at least a switched (ON) parallel resonant circuit that presents a high impedance load to the transmitter, and in the reception mode, both the series switch and the switch for the parallel resonant circuit are (OFF) to prevent signal loss, the series switch including electrostatic discharge (ESD) protection circuitry comprising a plurality of diodes connected between a gate and drain, and gate and source, of the series switch; and

a high-Q matching network, comprising one or more elements external to the transceiver integrated circuit and connected between the antenna and the receiver signal path, the one or more elements comprising at least an external LNA input inductor resonating with a capacitance of the parallel resonant circuit at a transmission frequency of interest so that minimal transmit power is dissipated in the receiver signal path.

10. A system comprising a communications transceiver, as per claim 9 , wherein the receiver signal path further comprises an LNA and the high-Q matching network connects to an input of the LNA through an input port of the transceiver integrated circuit.

11. A system comprising a communications transceiver, as per claim 10 , wherein the external LNA input inductor of the high-Q matching network comprises an external high-Q discrete inductor.

12. A system comprising a communications transceiver, as per claim 9 , wherein the antenna, external to the transceiver integrated circuit, is selectively connected to the transmitter or receiver signal path by an external transmit/receive (TR) switch.

13. A system comprising a communications transceiver, as per claim 9 , wherein the diodes are placed in one or more deep-n wells.

14. A communications transceiver, comprising:

a transceiver integrated circuit comprising a transmitter signal path comprising at least a transmitter, power amplifier, series switch and output port and a receiver signal path comprising at least a receiver, low-noise amplifier and switched parallel resonant circuit, the series switch including electrostatic discharge (ESD) protection circuitry comprising a plurality of diodes connected between a gate and drain, and gate and source, of the series switch;

an antenna, external to the transceiver integrated circuit, selectively connected in a transmission mode to the transmitter signal path and in reception mode to the receiver signal path; and

a high-Q matching network, comprising one or more elements external to the transceiver integrated circuit and connected between the antenna and the receiver signal path, the one or more elements comprising at least an external LNA input inductor resonating with a capacitance of the switched parallel resonant circuit at a transmission frequency of interest providing a high impedance load to the transmitter so that minimal transmit power is dissipated in the receiver signal path.

15. A communications transceiver, as per claim 14 , wherein the external LNA input inductor of the high-Q matching network comprises an external high-Q discrete inductor.

16. A communications transceiver, as per claim 14 , wherein the antenna, external to the transceiver integrated circuit, is selectively connected to the transmitter or receiver signal path by an external transmit/receive (TR) switch.

17. A communications transceiver, as per claim 14 , wherein the antenna is selectively connected, in the transmission mode, to the transmitter signal path by the series switch (ON) and is isolated from the receiver signal path by at least the switched parallel resonant circuit (ON) that presents a high impedance load to the transmitter, and in the reception mode, both the series switch and the switch for the parallel resonant circuit are (OFF) to prevent signal loss.

18. A communications transceiver, as per claim 14 , wherein the high-Q matching network comprises a resonating capacitor coupled to the external LNA input inductor.

19. A communications transceiver, as per claim 14 , wherein the diodes are placed in one or more deep-n wells.

20. A communications transceiver, as per claim 14 , wherein the communications transceiver is part of an RF transceiver, user equipment (UE) transceiver, base station (BS) transceiver, wireless transceiver, LTE transceiver or MIMO transceiver.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE PATENT NUMBER 9,385,856 TO 9,385,756 PREVIOUSLY RECORDED AT REEL: 47349 FRAME: 001. ASSIGNOR(S) HEREBY CONFIRMS THE MERGER. Recorded Mar 22, 2019
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 051144/0648 →
CORRECTIVE ASSIGNMENT TO CORRECT THE EFFECTIVE DATE PREVIOUSLY RECORDED ON REEL 047229 FRAME 0408. ASSIGNOR(S) HEREBY CONFIRMS THE THE EFFECTIVE DATE IS 09/05/2018. Recorded Oct 29, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047349/0001 →
MERGER Recorded Oct 4, 2018
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: AVAGO TECHNOLOGIES INTERNATIONAL SALES PTE. LIMITED
Reel/Frame 047229/0408 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: BROADCOM CORPORATION
Reel/Frame 041712/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 1, 2017
From: BROADCOM CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041706/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: BROADCOM CORPORATION
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037806/0001 →