Synchronous global controller for enhanced pipelining
View Patent ↗A system includes a memory block and a controller. The controller is adapted to skew a pre-charge signal for a bit line of the memory block. The controller can skew the pre-charge signal during a read operation or a write operation. The system can also include a sense amplifier in communication with a bit line of the memory block, and the sense amplifier can automatically shut off after indicating a sensed data state for the bit line. The controller may be a global controller or a local controller.
1. A system comprising:
a memory block; and
a controller in communication with the memory block, the controller adapted to skew a pre-charge signal for a bit line of the memory block.
2. The system of claim 1 , where the controller is adapted to skew the pre-charge signal for performing a read operation of the memory block.
3. The system of claim 1 , where the controller is adapted to skew the pre-charge signal for performing a write operation of the memory block.
4. The system of claim 1 , further comprising:
a sense amplifier in communication with the bit line of the memory block, the sense amplifier adapted to:
automatically shut off after indicating a sensed data state for the bit line.
5. The system of claim 4 , where the sense amplifier comprises a self-latching sense amplifier.
6. The system of claim 4 , where the controller is adapted to precharge the bit line in response to the sense amplifier shutting off.
7. The system of claim 1 , where the controller is adapted to keep the bit line precharged when the bit line is not selected during a memory access.
8. The system of claim 1 , where the controller comprises a global controller.
9. The system of claim 1 , where the controller comprises a local controller.
10. The system of claim 9 , where the local controller comprises an asynchronously controlled local controller.
11. The system of claim 1 , where the controller comprises a local controller adapted to receive a timing signal from a global controller that is in communication with other local controllers.
12. A method comprising:
through a controller in communication with a memory block:
skewing a pre-charge signal for a bit line of the memory block.
13. The method of claim 12 , where skewing comprises:
skewing the pre-charge signal for a read operation of the memory block.
14. The method of claim 12 , where skewing comprises:
skewing the pre-charge signal for a write operation of the memory block.
15. The method of claim 12 , further comprising:
automatically shutting off a sense amplifier in communication with the bit line after indicating a sensed data state for the bit line.
16. The method of claim 15 , where skewing the pre-charge signal comprises precharging the bit line in response to the sense amplifier shutting off.
17. The method of claim 12 , where skewing the pre-charge signal comprises:
skewing the pre-charge signal through asynchronous logic.
18. The method of claim 12 , where skewing the pre-charge signal comprises:
skewing the pre-charge signal through synchronous logic.
19. A system comprising:
a first controller in communication with a first memory block that comprises a first pre-charge signal; and
a second controller in communication with a second memory block that comprises a second pre-charge signal;
where the first and second controllers are adapted to independently skew the first and second pre-charge signals.
20. The system of claim 19 , further comprising:
a global controller in communication with the first and second controllers; and
where the first and second controllers each comprise a local controller that is adapted to receive a timing signal from the global controller.