Boot State Restore from Nonvolatile Bitcell Array

1 . A computing device apparatus providing non-volatile logic based computing, the apparatus comprising:

a plurality of non-volatile logic element arrays;

a plurality of volatile storage elements;

at least one non-volatile logic controller configured to control the plurality of non-volatile logic element arrays to store a machine state represented by the plurality of volatile storage elements and to read out a stored machine state from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements;

wherein at least one of the plurality of non-volatile logic element arrays is configured to store a boot state representing a state of the computing device apparatus after a given amount of a boot process is completed;

wherein the at least one non-volatile logic controller is configured to control restoration of data representing the boot state from the at least one of the plurality of non-volatile logic element arrays to corresponding ones of the plurality of volatile storage elements in response to detecting a reset event for the computing device apparatus.

2 . The computing device apparatus of claim 1 wherein individual ones of the plurality of non-volatile logic element arrays comprise ferroelectric capacitor based bit cells.

3 . The computing device apparatus of claim 2 wherein the at least one non-volatile logic controller is configured to execute a round-trip data restoration operation that automatically writes back data to an individual non-volatile logic element after reading data from the individual non-volatile logic element without completing separate read and write operations.

4 . The computing device apparatus of claim 2 wherein the at least one non-volatile logic controller is configured to execute the round-trip data restoration by:

initiating reading of data from the individual non-volatile logic element at a first time by switching a first plate line high;

at a second time switching a sense amplifier enable signal high;

at a third time switching a pass line high;

at a fourth time switching a second plate line high.

5 . The computing device apparatus of claim 4 wherein the individual non-volatile logic element is configured to have a voltage induced on a node of a corresponding ferroelectric capacitor bit cell based on a capacitance ratio for ferroelectric capacitors of the corresponding ferroelectric capacitor bit cell.

6 . The computing device apparatus of claim 5 wherein the individual non-volatile logic element is configured to enable a sense amplifier to detect the voltage induced on the node in response to switching the sense amplifier enable signal high.

7 . The computing device apparatus of claim 6 wherein the individual non-volatile logic element is configured to open transfer gates by switching the pass line high to provide an output signal corresponding to data stored in the individual non-volatile logic element.

8 . The computing device apparatus of claim 6 wherein the individual non-volatile logic element is configured to induce a polarizing signal across the ferroelectric capacitors to write data back to the corresponding ferroelectric capacitor bit cell corresponding to the data stored in the individual non-volatile logic element by the switching high of the second plate line.

9 . The computing device apparatus of claim 4 wherein the at least one non-volatile logic controller is configured to return the individual non-volatile logic element to a non-volatile storage state by:

at a fifth time switching the first plate line and the second plate line low;

at a sixth time switching the pass line low;

at a seventh time switching the sense amplifier enable signal low.

10 . The computing device apparatus of claim 4 wherein the at least one non-volatile logic controller is further configured to at the first time switching a clear signal from high to low to unclamp aspects of the individual non-volatile logic element from electrical ground.

11 . The computing device apparatus of claim 10 wherein the at least one non-volatile logic controller is further configured to at the seventh time switching a clear signal from low to high to clamp the aspects of the individual non-volatile logic element to the electrical ground.

12 . A method comprising:

operating a processing device using a plurality of volatile storage elements to execute a boot process for the processing device;

storing in a plurality of non-volatile logic element arrays a boot state representing a state of the processing device after a given amount of the boot process is completed;

restoring the boot state from the at least one of the plurality of non-volatile logic element arrays to corresponding ones of the plurality of volatile storage elements in response to detecting a reset event for the processing device.

13 . The method of claim 12 further comprising executing a round-trip data restoration operation that automatically writes back data to an individual non-volatile logic element after reading data from the individual non-volatile logic element without completing separate read and write operations.

14 . The method of claim 13 wherein the executing the round-trip data restoration operation further comprises:

initiating reading of data from the individual non-volatile logic element at a first time by switching a first plate line high to induce a voltage on a node of a corresponding ferroelectric capacitor bit cell based on a capacitance ratio for ferroelectric capacitors of the corresponding ferroelectric capacitor bit cell;

at a second time switching a sense amplifier enable signal high to enable a sense amplifier to detect the voltage induced on the node and to provide an output signal corresponding to data stored in the individual non-volatile logic element;

at a third time switching a pass line high to open transfer gates to provide an output signal corresponding to data stored in the individual non-volatile logic element;

at a fourth time switching a second plate line high to induce a polarizing signal across the ferroelectric capacitors to write data back to the corresponding ferroelectric capacitor bit cell corresponding to the data stored in the individual non-volatile logic element.

15 . The method of claim 14 further comprising returning the individual non-volatile logic element to a non-volatile storage state by:

at a fifth time switching the first plate line and the second plate line low;

at a sixth time switching the pass line low;

at a seventh time switching the sense amplifier enable signal low.

16 . The method of claim 14 further comprising at the first time switching a clear signal from high to low to unclamp aspects of the individual non-volatile logic element from electrical ground.

17 . The method of claim 16 further comprising at the seventh time switching a clear signal from low to high to clamp the aspects of the individual non-volatile logic element to the electrical ground.

18 . A computing device apparatus providing non-volatile logic based computing, the apparatus comprising:

a plurality of non-volatile logic element arrays wherein individual ones of the plurality of non-volatile logic element arrays comprise ferroelectric capacitor based bit cells;

a plurality of volatile storage elements;

at least one non-volatile logic controller configured to control the plurality of non-volatile logic element arrays to store a machine state represented by the plurality of volatile storage elements and to read out a stored machine state from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements;

wherein at least one of the plurality of non-volatile logic element arrays is configured to store a boot state representing a state of the computing device apparatus after a given amount of a boot process is completed;

wherein the at least one non-volatile logic controller is configured to, in response to detecting a previous system reset or power loss event for the computing device apparatus, control restoration of data representing the boot state from the at least one of the plurality of non-volatile logic element arrays to corresponding ones of the plurality of volatile storage elements using a round-trip data restoration operation that automatically writes back data to an individual non-volatile logic element after reading data from the individual non-volatile logic element without completing separate read and write operations;

wherein the at least one non-volatile logic controller is configured to execute the round-trip data restoration by:

initiating reading of data from the individual non-volatile logic element at a first time by switching a first plate line high to induce a voltage on a node of a corresponding ferroelectric capacitor bit cell based on a capacitance ratio for ferroelectric capacitors of the corresponding ferroelectric capacitor bit cell;

at a second time switching a sense amplifier enable signal high to enable a sense amplifier to detect the voltage induced on the node and to provide an output signal corresponding to data stored in the individual non-volatile logic element;

at a third time switching a pass line high to open transfer gates to provide an output signal corresponding to data stored in the individual non-volatile logic element;

at a fourth time switching a second plate line high to induce a polarizing signal across the ferroelectric capacitors to write data back to the corresponding ferroelectric capacitor bit cell corresponding to the data stored in the individual non-volatile logic element.

19 . The computing device apparatus of claim 18 wherein the at least one non-volatile logic controller is configured to return the individual non-volatile logic element to a non-volatile storage state by:

at a fifth time switching the first plate line and the second plate line low;

at a sixth time switching the pass line low;

at a seventh time switching the sense amplifier enable signal low.

20 . The computing device apparatus of claim 18 wherein the at least one non-volatile logic controller is further configured to:

at the first time switching a clear signal from high to low to unclamp aspects of the individual non-volatile logic element from electrical ground;

at the seventh time switching a clear signal from low to high to clamp the aspects of the individual non-volatile logic element to the electrical ground.