Configuration bit sequencing control of nonvolatile domain and array wakeup and backup
A processing device includes a plurality of non-volatile logic element array domains having two or more non-volatile logic element arrays to store 2006 a machine state of the processing device stored in a plurality of volatile store elements. Configuration bits are read to direct which non-volatile logic element array domains are enabled first and to direct an order in which the first enabled non-volatile logic element array domains are restored or backed up in response to entering a wakeup or backup mode. Configuration bits can be read to direct an order of and a parallelism of how individual non-volatile logic element arrays in a first enabled non-volatile logic element array domain are restored or backed up. The order of restoration or backing up can be controlled by instructions from non-volatile arrays of the first enabled of the plurality of non-volatile logic element array domains.
1. A computing device apparatus providing non-volatile logic based computing, the apparatus comprising:
a plurality of non-volatile logic element array domains wherein at least one of the non-volatile logic element array domains comprises two or more non-volatile logic element arrays;
a plurality of volatile storage elements;
at least one non-volatile logic controller configured to control the plurality of non-volatile logic element array domains to store a machine state represented by the plurality of volatile storage elements and to read out a stored machine state from the plurality of non-volatile logic element array domains to the plurality of volatile storage elements;
wherein the at least one non-volatile logic controller is further configured to read configuration bits that direct which of the plurality of non-volatile logic element array domains are enabled first in response to the computing device apparatus's entering a wakeup or backup mode;
wherein the at least one non-volatile logic controller is further configured to read configuration bits that direct an order in which the first enabled of the plurality of non-volatile logic element array domains are restored or backed up in response to the computing device apparatus's entering a wakeup or backup mode;
wherein individual non-volatile arrays of the ones of the first enabled of the plurality of non-volatile logic element array domains include instructions for an order in which other non-volatile logic element arrays are to be restored next;
wherein the at least one non-volatile logic controller is further configured to control an order in which the first enabled of the plurality of non-volatile logic element array domains are restored or backed up in response to the instructions from the individual non-volatile arrays of the ones of the first enabled of the plurality of non-volatile logic element array domains.
2. A method comprising:
operating a processing device using a plurality of volatile storage elements to execute at least one function;
storing in a plurality of non-volatile logic element array domains, wherein at least one of the non-volatile logic element array domains comprises two or more non-volatile logic element arrays, a machine state of the processing device stored in the plurality of volatile store elements in response to the processing device entering a backup mode;
reading configuration bits to direct which of the plurality of non-volatile logic element array domains are enabled first in response to the processing device's entering a wakeup or backup mode;
reading configuration bits to direct an order in which the first enabled of the plurality of non-volatile logic element array domains are restored or backed up in response to the computing device apparatus's entering a wakeup or backup mode;
controlling the order of restoration or backing up in response to instructions from the individual non-volatile arrays of the ones of the first enabled of the plurality of non-volatile logic element array domains.
3. A method comprising:
operating a processing device using a plurality of volatile storage elements to execute at least one function;
storing in a plurality of non-volatile logic element array domains, wherein at least one of the non-volatile logic element array domains comprises two or more non-volatile logic element arrays, a machine state of the processing device stored in the plurality of volatile store elements in response to the processing device entering a backup mode;
reading configuration bits to direct which of the plurality of non-volatile logic element array domains are enabled first in response to the processing device's entering a wakeup or backup mode;
reading configuration bits to direct an order in which the first enabled of the plurality of non-volatile logic element array domains are restored or backed up in response to the computing device apparatus's entering a wakeup or backup mode;
reading configuration bits to direct an order of and whether and which individual ones of the two or more non-volatile logic element arrays in at least one of the first enabled of the plurality of non-volatile logic element array domains to restore or backup in parallel in response to the processing device's entering a wakeup or backup mode;
controlling the order of restoration or backing up in response to instructions from the individual non-volatile arrays of the ones of the first enabled of the plurality of non-volatile logic element array domains.
4. The method of claim 3 further comprising associating individual ones of the at least one function with individual ones of the plurality of non-volatile logic element arrays.
5. The method of claim 3 wherein the associating the at least one function with individual ones of the plurality of non-volatile logic element arrays further comprises designating any one of a plurality of peripheral functions for the processing device.