Processing Device With Restricted Power Domain Wakeup Restore From Nonvolatile Logic Array

1 . A computing device apparatus providing non-volatile logic based computing, the apparatus comprising:

a plurality of non-volatile logic element arrays;

a plurality of volatile storage elements;

at least one non-volatile logic controller configured to control the plurality of non-volatile logic element arrays to store a machine state represented by the plurality of volatile storage elements and to read out a stored machine state from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements;

wherein the at least one non-volatile logic controller is further configured to store first program data from a first program executed by the computing device apparatus in a first set of non-volatile logic element arrays of the plurality of non-volatile logic element arrays;

wherein the at least one non-volatile logic controller is further configured to store second program data from a second program executed by the computing device apparatus in a second set of non-volatile logic element arrays of the plurality of non-volatile logic element arrays;

wherein the at least one non-volatile logic controller is further configured to restore the first program data or the second program data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements in response to receiving a stimulus regarding whether the first program or the second program is to be executed by the computing device apparatus.

2 . The computing device apparatus of claim 1 wherein the at least one non-volatile logic controller is further configured to store the first program data or the second program data to the plurality of non-volatile logic element arrays in response to receiving a stimulus regarding an interrupt for the computing device apparatus.

3 . The computing device apparatus of claim 2 wherein the at least one non-volatile logic controller is further configured to restore either the first program data or the second program data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements based upon a type of the interrupt for the computing device apparatus.

4 . The computing device apparatus of claim 1 wherein the first program and the second program correspond to distinct executing threads or virtual machines for the computing device apparatus.

5 . The computing device apparatus of claim 1 further comprising a multiplexer connected to variably connect individual ones of the volatile storage elements to one or more corresponding individual ones of the non-volatile logic element arrays.

6 . The computing device apparatus of claim 5 further comprising wherein the at least one non-volatile logic controller is further configured to store the first program data or the second program data to the plurality of non-volatile logic element arrays by controlling the multiplexer to connect individual ones of the plurality of volatile storage elements to either the first set of non-volatile logic element arrays or the second set of non-volatile logic element arrays based on whether the first program or the second program is executing in the computing device apparatus.

7 . The computing device apparatus of claim 1 further comprising a multiplexer connected to variably connect outputs of individual ones of the non-volatile logic element arrays to inputs of one or more corresponding individual ones of the volatile storage elements.

8 . The computing device apparatus of claim 7 further comprising wherein the at least one non-volatile logic controller is further configured to restore the first program data or the second program data to the plurality of volatile storage elements by controlling the multiplexer to connect inputs of individual ones of the plurality of volatile storage elements to outputs of either the first set of non-volatile logic element arrays or the second set of non-volatile logic element arrays based on whether the first program or the second program is to be executed in the computing device apparatus.

9 . The computing device apparatus of claim 1 wherein the at least one non-volatile logic controller is further configured to store the first program data or the second program data to the plurality of non-volatile logic element arrays in response to a power supply quality problem for the computing device apparatus.

10 . A method comprising:

operating a processing device having at least a first processing thread and a second processing thread using a plurality of volatile storage elements;

storing first program data stored in the plurality of volatile storage elements during execution of the first processing thread in a first set of non-volatile logic element arrays of a plurality of non-volatile logic element arrays;

storing second program data stored in the plurality of volatile storage elements during execution of the second processing thread in a second set of non-volatile logic element arrays of the plurality of non-volatile logic element arrays;

restoring the first program data or the second program data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements in response to receiving a stimulus regarding whether the first processing thread or the second processing thread is to be executed.

11 . The method of claim 10 further comprising storing the first program data or the second program data to the plurality of non-volatile logic element arrays in response to an interrupt for the processing device.

12 . The method of claim 11 further comprising restoring either the first program data or the second program data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements based upon a type of the interrupt for the processing device.

13 . The method of claim 10 further comprising storing the first program data or the second program data to the plurality of non-volatile logic element arrays by controlling a multiplexer to connect individual ones of the plurality of volatile storage elements to either the first set of non-volatile logic element arrays or the second set of non-volatile logic element arrays based on whether the first processing thread or the second processing thread is executing in the processing device.

14 . The method of claim 13 further comprising storing the first program data or the second program data to the plurality of non-volatile logic element arrays in response to a power supply quality problem for the processing device.

15 . A method comprising:

operating a processing device having at least a first processing thread and a second processing thread using a plurality of volatile storage elements;

in response to an interrupt for the processing device, executing one of:

storing first program data stored in the plurality of volatile storage elements during execution of the first processing thread in a first set of non-volatile logic element arrays of a plurality of non-volatile logic element arrays in response to an interrupt, or

storing second program data stored in the plurality of volatile storage elements during execution of the second processing thread in a second set of non-volatile logic element arrays of the plurality of non-volatile logic element arrays;

restoring the first program data or the second program data from the plurality of non-volatile logic element arrays to the plurality of volatile storage elements in response to receiving a stimulus regarding whether the first processing thread or the second processing thread is to be executed and based upon a type of the interrupt for the processing device;

storing the first program data or the second program data to the plurality of non-volatile logic element arrays in response to a power supply quality problem for the processing device.