Changing memory access for instruction based on memory access misses
View Patent ↗A non-transitory computer-readable storage medium may include instructions stored thereon. When executed by at least one processor, the instructions may be configured to cause a computing system to at least maintain a count of memory misses associated with an instruction, the instruction being included in code associated with an application, and grant the instruction direct access to memory, bypassing an operating system running on the computer, based on the count of memory misses meeting or exceeding a threshold.
1. A non-transitory computer-readable storage medium comprising instructions stored thereon that, when executed by at least one processor, are configured to cause a computing system to at least:
maintain a count of memory misses associated with an instruction, the instruction being included in code associated with an application; and
grant the instruction direct access to memory, bypassing an operating system running on the computer, based on the count of memory misses meeting or exceeding a threshold.
2. The storage medium of claim 1 , wherein the maintaining the count includes maintaining the count of page faults associated with an instruction pointer (IP), the IP determining which instruction in the code is executed.
3. The storage medium of claim 1 , wherein the memory misses include page faults.
4. The storage medium of claim 1 , wherein the granting the instruction direct access to memory includes switching a page table used by a program executing the instruction from an operating system to user space.
5. The storage medium of claim 1 , wherein the granting the instruction direct access to memory includes granting the instruction direct access to memory external to the computing device.
6. The storage medium of claim 1 , wherein the granting the instruction direct access to memory includes granting the instruction direct access to flash memory external to the computing device.
7. The storage medium of claim 1 , wherein the granting the instruction direct access to memory includes switching a thread of the instruction.
8. The storage medium of claim 1 , further comprising:
determining whether data accessed by the instruction is stored within a particular memory device,
wherein the granting the instruction direct access to memory includes granting the instruction direct access to memory, bypassing the operating system running on the computer, based on:
the count of memory misses meeting or exceeding the threshold; and
determining that the data accessed by the instruction is not stored within the particular memory device.
9. A non-transitory computer-readable storage medium comprising instructions stored thereon that, when executed by at least one processor, are configured to cause a computing system to at least:
maintain a count of memory misses associated with an instruction, the instruction being included in code associated with an application and including an operating system call to read data; and
modify the instruction, based on the count of memory misses associated with the instruction meeting or exceeding a threshold, so that the instruction includes a read of the data directly from a memory device instead of the operating system call.
10. The storage medium of claim 9 , wherein the modifying the instruction includes modifying the instruction so that the instruction includes a read of the data directly from a flash memory device.
11. The storage medium of claim 9 , wherein the modifying includes recompiling code, the code including the instruction, so that the instruction includes a read of the data directly from the memory device instead of the operating system call, based on the count of memory misses associated with the instruction meeting or exceeding the threshold.
12. The storage medium of claim 9 , wherein the modifying includes patching a binary code version of the instruction.
13. The storage medium of claim 9 , wherein the modifying includes switching a thread of the instruction.
14. An apparatus comprising:
at least one processor; and
at least one non-transitory computer-readable storage medium comprising instructions stored thereon that, when executed by at the least one processor, are configured to cause the apparatus to at least:
maintain a count of memory misses associated with an instruction, the instruction being included in code associated with an application; and
grant the instruction direct access to memory, bypassing an operating system running on the computer, based on the count of memory misses meeting or exceeding a threshold.
15. The apparatus of claim 14 , wherein the memory misses include page faults.
16. The apparatus of claim 14 , wherein the granting the instruction direct access to memory includes switching a page table used by a program executing the instruction from an operating system to user space.
17. The apparatus of claim 14 , wherein the granting the instruction direct access to memory includes granting the instruction direct access to memory external to the computing device.
18. The apparatus of claim 14 , wherein the granting the instruction direct access to memory includes granting the instruction direct access to flash memory external to the computing device.
19. The apparatus of claim 14 , wherein the granting the instruction direct access to memory includes switching a thread of the instruction.
20. The apparatus of claim 14 , further comprising:
determining whether data accessed by the instruction is stored within a particular memory device,
wherein the granting the instruction direct access to memory includes granting the instruction direct access to memory, bypassing the operating system running on the computer, based on:
the count of memory misses meeting or exceeding the threshold; and
determining that the data accessed by the instruction is not stored within the particular memory device.