IP Library Granted Patent US 8,923,061
Granted Patent B2
US 8,923,061 · App. 13/773,291 · Granted Dec 30, 2014

Programming method of nonvolatile memory device

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 8,923,061
App. No.
13/773,291
Granted
Dec 30, 2014
Kind
B2
Abstract

Provided is a programming method of a nonvolatile memory device which includes a plurality of strings each including a source select transistor, a plurality of memory cells, and a drain select transistor which are connected in series between a common source line and a bit line. The programming method includes: applying a first voltage to the common source line during a first period in which a channel of a plurality of memory cells of an unselected string is floated; and applying a second voltage increased more than the first in voltage to the common source line during a second period in which a selected memory cell is programmed, when a selected word line belongs to a word line group adjacent to the common source line.

Claims (26)

1. A programming method for a nonvolatile memory device that includes a plurality of strings, each including a source select transistor, a plurality of memory cells, and a drain select transistor that are connected in series between a common source line and a bit line, the programming method comprising:

applying a first voltage to the common source line during a first period in which a channel of a plurality of memory cells of an unselected string is floated;

applying a second voltage to an unselected bit line during the first period;

applying, when a selected word line belongs to a first word line group adjacent to the common source line, a third voltage that is greater than the first voltage to the common source line during a second period in which a selected memory cell is programmed; and

applying, when the selected word line belongs to a second word line group adjacent to the bit line, a fourth voltage that is greater than the second voltage to the unselected bit line during the second period.

2. The programming method of claim 1 , where the second period comprises:

a program voltage application period in which a program voltage is applied to the selected word line,

the third voltage is applied to the common source line during the program voltage application voltage, and

the fourth voltage is applied to the unselected bit line during the program voltage application voltage.

3. The programming method of claim 1 , where the second period comprises:

a pass voltage application period in which a pass voltage is applied to the selected word line, and

a program voltage application period in which a program voltage is applied to the selected word line, and

where the third voltage is applied to the common source line during the program voltage application period, and

where the fourth voltage is applied to the unselected bit line during the program voltage application period.

4. The programming method of claim 3 , where the third voltage is applied to the common source line during the pass voltage application period, and

the fourth voltage is applied to the unselected bit line during the pass voltage application period.

5. The programming method of claim 1 , where the first word line group comprises:

one or more word lines arranged from a side that is closest to the common source line, and

the second word line group comprises one or more word lines arranged from a side which is the most adjacent to the bit line.

6. The programming method of claim 5 , wherein the first and second word line groups are set independently of each other.

7. The programming method of claim 1 , where the first word line group is divided into first to Nth sub-groups arranged from a side that is closest to the common source line, where N is a natural number equal to or more than one,

where each of the first to Nth sub-groups comprises one or more word lines, and

where the magnitude of the third voltage decreases from the first sub-group to the N-th sub-group among the sub-groups to which the selected word line belongs.

8. The programming method of claim 1 , where the second word line group is divided into first to M-th sub-groups arranged from a side which is the most adjacent to the bit line where M is a natural number equal to or more than one,

where each of the first to M-th sub-groups comprises one or more word lines, and

where the magnitude of the fourth voltage decreases from the first sub-group to the M-th sub-group, among the sub-groups to which the selected word line belongs.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 7, 2024
From: SK HYNIX INC.
To: MIMIRIP LLC
Reel/Frame 067335/0246 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 21, 2013
From: KIM, TAE-GYUN
To: SK HYNIX INC.
Reel/Frame 029852/0915 →