Precision Exception Signaling for Multiple Data Architecture
Methods and systems that perform one or more operations on a plurality of elements using a multiple data processing element processor are provided. An input vector comprising a plurality of elements is received by a processor. The processor determines if performing a first operation on a first element will cause an exception and if so, writes an indication of the exception caused by the first operation to a first portion of an output vector stored in an output register. A second operation can be performed on a second element with the result of the second operation being written to a second portion of the output vector stored in the output register.
1 . A method of performing one or more operations on a plurality of elements using a multiple data processing element processor, comprising:
receiving one or more input vectors, wherein the one or more input vectors comprise a first set of elements and a second set of elements;
determining that performing a first operation on the first set of elements will cause an exception;
writing an indication of the exception caused by the first operation to a first element of an output vector,
performing a second operation on the second set of elements; and
writing a result of the second operation to a second element of the output vector.
2 . The method of claim 1 , further comprising determining that a non-signaling exception mode is enabled in the processor.
3 . The method of claim 1 , wherein the one or more input vectors comprise a third set of elements.
4 . The method of claim 3 , further comprising determining that performing a third operation on the third set of elements will cause an exception and writing an indication of the exception to a third element of the output vector.
5 . The method of claim 1 , wherein the first and second operations are the same operation.
6 . The method of claim 1 , wherein the multiple data processing element processor is a single input multiple data (SIMD) processor.
7 . The method of claim 1 , wherein the multiple data processing element processor is a multiple input multiple data (MIMD) processor.
8 . The method of claim 1 , wherein the indication signals an exception handler to handle the exception.
9 . The method of claim 1 , wherein each of the first and second sets of elements contains a single element.
10 . The method of claim 1 , wherein each of the first and second sets of elements contains a plurality of elements.
11 . A multiple data processing element system, comprising:
an input register configured to store one or more input vectors, wherein the one or more input vectors comprise a first set of elements and a second set of elements;
an output register configured to store the results of a plurality of operations; and
a multiple data processing element processor configured to:
receive the one or more input vectors from the input register,
determine that performing a first operation on the first set of elements will cause an exception and output an indication of the exception caused by the first operation to a first element of the output register, and
perform a second operation on a second set of elements and output the result of the operation to a second element of the output register.
12 . The system of claim 11 , wherein the processor is further configured to determine that a non-signaling exception mode is enabled in the processor.
13 . The system of claim 11 , wherein the one or more input vectors further comprise a third set of elements.
14 . The system of claim 13 , wherein the processor is further configured to determine that performing a third operation on the third set of elements will cause an exception and to output an indication of the exception to a third element of the output register.
15 . The system of claim 11 , wherein the first and second operations are the same operation.
16 . The system of claim 11 , wherein the multiple data processing element processor is a single input multiple data (SIMD) processor.
17 . The system of claim 11 , wherein the multiple data processing element processor is a multiple input multiple data (MIMD) processor.
18 . The method of claim 11 , wherein the indication is configured to signal an exception handler to handle the exception.
19 . The system of claim 11 , wherein each of the first and second sets of elements contains a single element.
20 . The system of claim 11 , wherein each of the first and second sets of elements contains a plurality of elements.