Semiconductor device
To reinforce power supply wirings without sacrificing the interconnectivity of semiconductor devices. When three wirings are formed in parallel in the same wiring layer and the center wiring among them is shorter than the outer wirings, a projecting portion integrated into the outer wiring is formed utilizing a free space remaining on the extension of the center wiring. For example, when the outer wirings are used as power supply wirings, the power supply wirings can be reinforced by adding the projecting portion. At this time, because the projecting portion is arranged in the free space, the interconnectivity is not sacrificed.
1. A semiconductor device, comprising:
a first wiring formed in a first wiring layer;
a second wiring formed along the first wiring in the first wiring layer;
a third wiring formed along the first and second wirings in a region between the first and second wirings of the first wiring layer;
a projecting portion formed in a region between the first and second wirings of the first wiring layer and integrated into the first wiring;
a fourth wiring formed in a second wiring layer, the fourth wiring intersecting with the first and second wirings and the projecting portion;
a fifth wiring formed in the second wiring layer, the fifth wiring intersecting with the first, second, and third wirings;
a first via group formed in an intersecting portion between the first wiring and the fourth wiring, the first via group coupling the first wiring and the fourth wiring;
a second via group formed in an intersecting portion between the second wiring and the fifth wiring, the second via group coupling the second wiring and the fifth wiring; and
a third via group formed in an intersecting portion between the projecting portion and the fourth wiring, the third via group coupling the projecting portion and the fourth wiring.
2. The semiconductor device according to claim 1 ,
the projecting portion being a first projecting portion, and
the semiconductor device further comprising:
a second projecting portion formed in a region between the first and second wirings of the first wiring layer and integrated into the second wiring;
a sixth wiring formed in the second wiring layer, the sixth wiring intersecting with the first and second wirings and the second projecting portion;
a fourth via group formed in an intersecting portion between the second wiring and the sixth wiring, the fourth via group coupling the second wiring and the sixth wiring; and
a fifth via group formed in an intersecting portion between the second projecting portion and the sixth wiring, the fifth via group coupling the second projecting portion and the sixth wiring.
3. The semiconductor device according to claim 1 ,
the projecting portion being also integrated with the second wiring, and
the semiconductor device further comprising:
a fourth via group formed in an intersecting portion between the first wiring and the fifth wiring, the fourth via group coupling the first wiring and the fifth wiring; and
a fifth via group formed in an intersecting portion between the second wiring and the fourth wiring, the fifth via group coupling the second wiring and the fourth wiring.
4. The semiconductor device according to claim 2 ,
wherein the first projecting portion and the second projecting portion are alternately arranged in a region between the first and second wirings.
5. The semiconductor device according to claim 2 , further comprising:
a seventh wiring formed along the sixth wiring in a region between the fourth and sixth wirings of the second wiring layer, the seventh wiring intersecting with the first and second wirings as well as the first and second projecting portions;
an eighth wiring formed along the fourth wiring in a region between the fourth and seventh wirings of the second wiring layer, the eighth wiring intersecting with the first and second wirings as well as the first and second projecting portions;
a sixth via group formed in an intersecting portion between the first wiring and the seventh wiring, the sixth via group coupling the first wiring and the seventh wiring;
a seventh via group formed in an intersecting portion between the first projecting portion and the seventh wiring, the seventh via group coupling the first projecting portion and the seventh wiring;
an eighth via group formed in an intersecting portion between the second wiring and the eighth wiring, the eighth via group coupling the second wiring and the eighth wiring; and
a ninth via group formed in an intersecting portion between the second projecting portion and the eighth wiring, the ninth via group coupling the second projecting portion and the eighth wiring,
wherein the first projecting portion includes a first intersecting portion intersecting with the fourth wiring, a second intersecting portion intersecting with the seventh wiring, and a collar portion formed between the first and second intersecting portions, and
wherein the second projecting portion includes a first intersecting portion intersecting with the sixth wiring, a second intersecting portion intersecting with the eighth wiring, and a collar portion formed between the first and second intersecting portions.
6. The semiconductor device according to claim 2 , further comprising:
a third projecting portion formed in a region between the first and second wirings of the first wiring layer and integrated into the second wiring;
a seventh wiring formed along the sixth wiring in a region between the fourth and sixth wirings of the second wiring layer, the seventh wiring intersecting with the first and second wirings and the first projecting portion;
an eighth wiring formed along the fourth wiring in a region outside of the fourth and sixth wirings of the second wiring layer, the eighth wiring intersecting with the first and second wirings and the third projecting portion;
a sixth via group formed in an intersecting portion between the first wiring and the seventh wiring, the sixth via group coupling the first wiring and the seventh wiring;
a seventh via group formed in an intersecting portion between the first projecting portion and the seventh wiring, the seventh via group coupling the first projecting portion and the seventh wiring;
an eighth via group formed in an intersecting portion between the second wiring and the eighth wiring, the eighth via group coupling the second wiring and the eighth wiring; and
a ninth via group formed in an intersecting portion between the third projecting portion and the eighth wiring, the ninth via group coupling the third projecting portion and the eighth wiring;
wherein the first projecting portion includes a first intersecting portion intersecting with the fourth wiring, a second intersecting portion intersecting with the seventh wiring, and a collar portion formed between the first and second intersecting portions.
7. The semiconductor device according to claim 2 , further comprising:
a third projecting portion formed in a region between the first and second wirings of the first wiring layer and integrated into the first wiring;
a fourth projecting portion formed in a region between the first and second wirings of the first wiring layer and integrated into the second wiring;
a seventh wiring formed along the sixth wiring in a region between the fourth and sixth wirings of the second wiring layer, the seventh wiring intersecting with the first and second wirings and the third projecting portion;
an eighth wiring formed along the fourth wiring in a region outside of the fourth and sixth wirings of the second wiring layer, the eighth wiring intersecting with the first and second wirings as well as the fourth projecting portion;
a sixth via group formed in an intersecting portion between the first wiring and the seventh wiring, the sixth via group coupling the first wiring and the seventh wiring;
a seventh via group formed in an intersecting portion between the third projecting portion and the seventh wiring, the seventh via group coupling the third projecting portion and the seventh wiring;
an eighth via group formed in an intersecting portion between the second wiring and the eighth wiring, the eighth via group coupling the second wiring and the eighth wiring; and
a ninth via group formed in an intersecting portion between the fourth projecting portion and the eighth wiring, the ninth via group coupling the fourth projecting portion and the eighth wiring,
wherein the third projecting portion includes a collar portion formed in a region between the seventh wiring and the eighth wiring of the first wiring layer, and
wherein the fourth projecting portion includes a collar portion formed in a region between the seventh wiring and the eighth wiring of the first wiring layer.
8. The semiconductor device according to claim 3 , further comprising:
a sixth wiring formed in the first wiring layer, the sixth wiring intersecting with the fourth and fifth wirings;
a seventh wiring formed along the sixth wiring in the first wiring layer; and
an eighth wiring formed along the sixth and seventh wirings in a region between the sixth and seventh wirings of the first wiring layer,
the projecting portion being a first projecting portion, and
the semiconductor device still further comprising:
a second projecting portion formed in a region between the sixth and seventh wirings of the first wiring layer, and integrated into the sixth and seventh wirings;
a ninth wiring formed in the second wiring layer, the ninth wiring intersecting with the first, second, fourth, and fifth wirings as well as the first and second projecting portions;
a tenth wiring formed in the second wiring layer, the tenth wiring intersecting with the first to sixth wirings;
a sixth via group formed in an intersecting portion between the sixth wiring and the ninth wiring, the sixth via group coupling the sixth wiring and the ninth wiring;
a seventh via group formed in an intersecting portion between the seventh wiring and the ninth wiring, the seventh via group coupling the seventh wiring and the ninth wiring;
an eighth via group formed in an intersecting portion between the second projecting portion and the ninth wiring, the eighth via group coupling the second projecting portion and the ninth wiring;
a ninth via group formed in an intersecting portion between the sixth wiring and the tenth wiring, the ninth via group coupling the sixth wiring and the tenth wiring; and
a tenth via group formed in an intersecting portion between the seventh wiring and the tenth wiring, the tenth via group coupling the seventh wiring and the tenth wiring.
9. The semiconductor device according to claim 8 , further comprising:
an eleventh wiring formed along the ninth wiring in a region between the fourth and ninth wirings of the second wiring layer, the eleventh wiring intersecting with the first, second, sixth, and seventh wirings as well as the first and second projecting portions;
a twelfth wiring formed along the fourth wiring in a region between the fourth and eleventh wirings of the second wiring layer, the twelfth wiring intersecting with the first, second, sixth, and seventh wirings as well as the first and second projecting portions;
an eleventh via group formed in an intersecting portion between the eleventh wiring, and the first and second wirings as well as the first projecting portion, the eleventh via group coupling the eleventh wiring, and the first and second wirings as well as the first projecting portion; and
a twelfth via group formed in an intersecting portion between the twelfth wiring, and the sixth and seventh wirings as well as the second projecting portion, the twelfth via group coupling the twelfth wiring, and the sixth and seventh wirings as well as the second projecting portion.
10. The semiconductor device according to claim 9 ,
wherein widths of the first, second, fourth, and fifth wirings are wider than widths of the third and sixth wirings.
11. The semiconductor device according to claim 2 , further comprising a memory cell coupled to the first, second, and third wirings,
wherein the first wiring is coupled to a first voltage source,
wherein the second wiring is coupled to a second voltage source, and
wherein the third wiring is coupled to a third voltage source.
12. The semiconductor device according to claim 8 , further comprising a memory cell coupled to the first, third, and fourth wirings,
wherein the first wiring is coupled to a first voltage source,
wherein the sixth wiring is coupled to a second voltage source, and
wherein the third wiring is coupled to a third voltage source.