Efficient low-latency buffer
View Patent ↗An efficient low latency buffer, and method of operation, is described. The efficient low latency buffer may be used as a bi-directional memory buffer in an audio playback device to buffer both output and input data. An application processor coupled to the bi-directional memory buffer is responsive to an indication to write data to the bi-directional memory buffer reads a defined size of input data from the bi-directional memory buffer. The input data read from the bi-directional memory buffer is replaced with output data of the defined size. In response to a mode-change signal, the defined size of data is changed that is read and written from and to the bi-directional memory buffer. The buffer may allow the application processor to enter a low-powered sleep mode more frequently.
1. An application processor for reading and writing data from and to a bi-directional memory buffer, the application processor configured to:
responsive to a first control signal indicating that data can be provided to the bi-directional memory buffer, read a predefined size of input data from the bi-directional memory buffer, and replace the input data read from the bi-directional memory buffer with output data of the predefined size;
responsive to a second control signal, change the predefined size of data that is read from and written to the bi-directional memory buffer; and
process the read input data to identify one or more control commands provided as one or more audio tones in the input data.
2. The application processor of claim 1 , further configured to receive the first control signal from the bi-directional memory buffer.
3. The application processor of claim 1 , further configured to generate the first control signal at a frequency inversely proportional to the defined size of data that is read from and written to the bi-directional memory buffer.
4. The application processor of claim 1 , wherein the first control signal is received via an analog-to-digital/digital-to-analog converter (ADDAC) control signal line.
5. The application processor of claim 1 , wherein the second control signal indicates one of a plurality of modes for the application processor to operate in, a first mode reading and writing a first size of data at a first rate, and a second mode reading and writing a second size of data greater than the first size of data at a second rate less than the first rate.
6. The application processor of claim 5 , wherein the second control signal is received via an analog-to-digital/digital-to-analog converter (ADDAC) control signal line.
7. The application processor of claim 1 , further configured to provide the second control signal to the bi-directional memory buffer.
8. The application processor of claim 1 , further configured to enter a low power sleep mode upon replacing the input data read from the bi-directional memory buffer with the output data, and to enter a high power awake mode upon receiving the first control signal.
9. A method in an application processor for reading and writing data from and to a bi-directional memory buffer, the method comprising:
responsive to a first control signal indicating that data can be provided to the bi-directional memory buffer, reading a predefined size of input data from the bi-directional memory buffer, and replacing the input data read from the bi-directional memory buffer with output data of the predefined size;
responsive to a second control signal, changing the predefined size of data that is read from and written to the bi-directional memory buffer; and
processing the read input data to identify one or more control commands provided as one or more audio tones in the input data.
10. The method of claim 9 , further comprising receiving the first control signal from the bi-directional memory buffer.
11. The method of claim 9 , further comprising generating the first control signal at a frequency inversely proportional to the defined size of data that is read from and written to the bi-directional memory buffer.
12. The method of claim 9 , further comprising processing the read input data to identify one or more control commands.
13. The method of claim 9 , wherein the second control signal indicates one of a plurality of modes for the application processor to operate in, a first mode reading and writing a first size of data at a first rate, and a second mode reading and writing a second size of data greater than the first size of data at a second rate less than the first rate.
14. The method of claim 13 , wherein the second control signal is received via an analog-to-digital/digital-to-analog converter (ADDAC) control signal line.
15. The method of claim 9 , further comprising entering a low power sleep mode upon replacing the input data read from the bi-directional memory buffer with the output data, and to enter a high power awake mode upon receiving the first control signal.
16. The method of claim 9 , further comprising providing the second control signal to the bi-directional memory buffer.
17. A non-transitory memory containing computer executable instructions for reading and writing data from and to a bi-directional memory buffer, the instructions comprising:
responsive to a first control signal indicating that data can be provided to the bi-directional memory buffer, reading a predefined size of input data from the bi-directional memory buffer, and replacing the input data read from the bi-directional memory buffer with output data of the predefined size;
responsive to a second control signal, changing the predefined size of data that is read from and written to the bi-directional memory buffer; and
processing the read input data to identify one or more control commands provided as one or more audio tones in the input data.