Adaptive architecture in a channel detector for NAND flash channels

1. A method for adjusting a threshold voltage in a read channel, comprising the steps of:

(A) setting a value of said threshold voltage based on an estimate;

(B) determining whether said read is successful;

(C) if said read is not successful, performing a plurality of reads with a varying value of said threshold voltage;

(D) reading a calibration value from a look-up table based on said plurality of reads; and

(E) setting said threshold value in response to said calibration value.

2. The method according to claim 1 , wherein said read channel is implemented in a memory.

3. The method according to claim 2 , wherein said memory comprises a flash memory.

4. The method according to claim 2 , wherein memory comprises a NAND flash memory.

5. The method according to claim 2 , wherein said memory comprises a plurality of modules.

6. The method according to claim 2 , wherein said memory comprises a solid state drive (SSD).

7. The method according to claim 1 , wherein said plurality of reads comprises a histogram.

8. The method according to claim 1 , wherein said look-up table comprises a log-likelihood ratio (LLR) table.

9. An apparatus comprising:

a memory configured to store data; and

a controller configured to process a plurality of input/output requests to read/write to/from said memory, wherein said controller is configured to (i) set a value of a threshold voltage based on an estimate, (ii) determine whether said read is successful, (iii) if said read is not successful, perform a plurality of reads with a varying value of said threshold voltage, (iv) read a calibration value from a look-up table based on said plurality of reads and (v) set said threshold value in response to said calibration value.

10. The apparatus according to claim 9 , wherein said apparatus calculates an error value used by an ECC decoder.

11. The apparatus according to claim 9 , wherein said memory includes a plurality of page signals each representing a bit sequence resulting from a plurality of reads at a plurality of voltages.

12. The apparatus according to claim 9 , wherein said memory comprises a flash memory.

13. The apparatus according to claim 9 , wherein (i) said look-up table stores a plurality of calibration values, and (ii) each of each said calibration values is retrieved in response to an index signal.

14. An apparatus comprising:

an interface configured to process a plurality of read/write operations to/from a memory; and

a control circuit configured to (i) set a value of a threshold voltage based on an estimate, (ii) determine whether said read operation is successful, (iii) if said read operation is not successful, perform a plurality of read operations with a varying value of said threshold voltage, (iv) read a calibration value from a look-up table based on said plurality of read operations and (v) set said threshold value in response to said calibration value.

15. The apparatus according to claim 14 , wherein said apparatus calculates an error value used by an ECC decoder.

16. The apparatus according to claim 14 , wherein said memory includes a plurality of page signals each representing a bit sequence resulting from a plurality of read operations at a plurality of voltages.

17. The apparatus according to claim 14 , wherein said memory comprises a flash memory.

18. The apparatus according to claim 14 , wherein (i) said look-up table stores a plurality of calibration values, and (ii) each of said calibration values is retrieved in response to an index signal.

19. The apparatus according to claim 14 , wherein said look-up table comprises a log-likelihood ratio (LLR) table.

20. The apparatus according to claim 14 , wherein said plurality of read operations comprises a histogram.