Reduced complexity reliability computations for flash memories

1. A method for processing data from a flash memory device that stores M bits per cell using 2^M possible states, comprising the steps of:

obtaining at least two soft read voltage values corresponding to two reference voltages V 0 and V 1 , wherein said two reference voltages V 0 and V 1 are between two adjacent states of said 2^M possible states; and

converting said at least two soft read voltage values to a log likelihood ratio for a region between said two reference voltages V 0 and V 1 using probability density functions only for said two adjacent states, wherein M is greater than one.

2. The method of claim 1 , wherein said probability density functions for each of said two adjacent states S n and S n+1 can be expressed as f(ν;μ n ,σ n 2 ) and f(ν;μ n+1 ,σ n+1 ), where said probability density functions are defined by a mean μ n and a variance σ n 2 and ν is the soft read voltage.

3. The method of claim 1 , wherein said log likelihood ratio for said region between said two reference voltages V 0 and V 1 is expressed as follows:

LLR

≈

ln

(

∫

V

0

V

1

⁢

f

⁡

(

v

;

μ

n

,

σ

n

2

)

⁢

⁢

ⅆ

v

∫

V

0

V

1

⁢

f

⁡

(

v

;

μ

n

+

1

,

σ

n

+

1

2

)

⁢

⁢

ⅆ

v

)

where f(ν, μ n , σ n 2 ) and f(ν;μ n+1 ,σ n+1 2 ) are probability density functions for said two adjacent states S n and S n+1 defined by a mean μ n and a variance σ n 2 and ν is the soft read voltage.

4. The method of claim 1 , wherein said log likelihood ratio for said region between said two reference voltages V 0 and V 1 is expressed as follows:

LLR

≈

ln

⁡

(

f

⁡

(

0.5

⁢

(

V

1

+

V

0

)

;

μ

n

,

σ

n

2

)

f

⁡

(

0.5

⁢

(

V

1

+

V

0

)

;

μ

n

+

1

,

σ

n

+

1

2

)

)

where f(0.5(V 1 +V 0 ); μ n , σ n 2 ) and f(0.5(V 1 +V 0 ); μ n+1 , σ n+1 2 ) are probability density functions for said two adjacent states S n and S n+1 defined by a mean μ n and a variance σ n 2 and ν is the soft read voltage.

5. The method of claim 1 , wherein said log likelihood ratio for said region between said two reference voltages V 0 and V 1 is expressed as follows:

LLR

=

ln

⁡

(

σ

n

+

1

)

-

ln

⁡

(

σ

n

)

+

(

V

-

μ

n

+

1

)

2

2

⁢

σ

n

+

1

2

-

(

V

-

μ

n

)

2

2

⁢

σ

n

2

where V is equal to 0.5(V 1 +V 0 ) and wherein said two adjacent states S n and S n+1 are defined by a mean ν n and a variance σ n 2 and ν is the soft read voltage.

6. The method of claim 1 , wherein said soft read voltage values comprise one or more of hard decision read values obtained by a plurality of read retries of a given cell at a plurality of reference voltages and soft values obtained from said flash memory device.

7. The method of claim 1 , further comprising the step of applying said log likelihood ratios to one or more of a soft decision decoder and a buffer.

8. A non-transitory machine-readable recordable storage medium, wherein one or more software programs when executed by one or more processing devices implement the steps of the method of claim 1 .

9. A flash controller for processing data from a flash memory device that stores M bits per cell using 2^M possible states, comprising:

a log likelihood ratio generation block configured to:

obtain at least two soft read voltage values corresponding to two reference voltages V 0 and V 1 , wherein said two reference voltages V 0 and V 1 are between two adjacent states of said 2^M possible states, wherein M is greater than one; and

convert said at least two soft read voltage values to a log likelihood ratio for a region between said two reference voltages V 0 and V 1 using probability density functions only for said two adjacent states.

10. The flash controller of claim 9 , wherein said probability density functions for each of said two adjacent states S n and S n+1 can be expressed as f(ν; μ n , σ n 2 ) and f(ν; μ n+1 ,σ n+1 2 ), where said probability density functions are defined by a mean μ n and a variance σ n 2 and ν is the soft read voltage.

11. The flash controller of claim 9 , wherein said log likelihood ratio for said region between said two reference voltages V 0 and V 1 is expressed as follows:

LLR

≈

ln

(

∫

V

0

V

1

⁢

f

⁡

(

v

;

μ

n

,

σ

n

2

)

⁢

⁢

ⅆ

v

∫

V

0

V

1

⁢

f

⁡

(

v

;

μ

n

+

1

,

σ

n

+

1

2

)

⁢

⁢

ⅆ

v

)

where f(ν; μ n , σ n 2 ) and f(ν; μ n+1 ,σ n+1 2 ) are probability density functions for said two adjacent states S n and S n+1 defined by a mean μ n and a variance σ n+1 and ν is the soft read voltage.

12. The flash controller of claim 9 , wherein said log likelihood ratio for said region between said two reference voltages V 0 and V 1 is expressed as follows:

LLR

≈

ln

⁡

(

f

⁡

(

0.5

⁢

(

V

1

+

V

0

)

;

μ

n

,

σ

n

2

)

f

⁡

(

0.5

⁢

(

V

1

+

V

0

)

;

μ

n

+

1

,

σ

n

+

1

2

)

)

where f(0.5(V 1 +V 0 ); μ n , σ n 2 ) and f(0.5(V 1 +V 0 ); μ n+1 , σ n+1 2 ) are probability density functions for said two adjacent states S n and S n+1 defined by a mean μ n and a variance σ n 2 and ν is the soft read voltage.

13. The flash controller of claim 9 , wherein said log likelihood ratio for said region between said two reference voltages V 0 and V 1 is expressed as follows:

LLR

=

ln

⁡

(

σ

n

+

1

)

-

ln

⁡

(

σ

n

)

+

(

V

-

μ

n

+

1

)

2

2

⁢

σ

n

+

1

2

-

(

V

-

μ

n

)

2

2

⁢

σ

n

2

where V is equal to 0.5(V 1 +V 0 ) and wherein said two adjacent states S n and S n+1 are defined by a mean μ n and a variance σ n 2 and ν is the soft read voltage.

14. The flash controller of claim 9 , wherein said soft read voltage values comprise one or more of hard decision read values obtained by a plurality of read retries of a given cell at a plurality of reference voltages and soft values obtained from said flash memory device.

15. The flash controller of claim 9 , wherein said log likelihood ratio generation block is further configured to apply said log likelihood ratios to one or more of a soft decision decoder and a buffer.

16. An integrated circuit, comprising:

a flash controller for processing data from a flash memory device that stores M bits per cell using 2^M possible states, comprising:

a log likelihood ratio generation block configured to:

obtain at least two soft read voltage values corresponding to two reference voltages V 0 and V 1 , wherein said two reference voltages V 0 and V 1 are between two adjacent states of said 2^M possible states, wherein M is greater than one; and

convert said at least two soft read voltage values to a log likelihood ratio for a region between said two reference voltages V 0 and V 1 using probability density functions only for said two adjacent states.

17. The integrated circuit of claim 16 , wherein said probability density functions for each of said two adjacent states S n and S n+1 can be expressed as f(ν;μ n ,σ n 2 ) and f(ν; μ n ,σ n+1 2 ), where said probability density functions are defined by a mean μ n and a variance σ n 2 and ν is the soft read voltage.

18. The integrated circuit of claim 16 , wherein said log likelihood ratio for said region between said two reference voltages V 0 and V 1 is expressed as follows:

LLR

≈

ln

(

∫

V

0

V

1

⁢

f

⁡

(

v

;

μ

n

,

σ

n

2

)

⁢

⁢

ⅆ

v

∫

V

0

V

1

⁢

f

⁡

(

v

;

μ

n

+

1

,

σ

n

+

1

2

)

⁢

⁢

ⅆ

v

)

where f(ν;μ n ,σ n 2 ) and f(ν; μ n+1 ,σ n+1 2 ) are probability density functions for said two adjacent states S n and S n+1 defined by a mean μ n and a variance σ n 2 and ν is the soft read voltage.

19. The integrated circuit of claim 16 , wherein said soft read voltage values comprise one or more of hard decision read values obtained by a plurality of read retries of a given cell at a plurality of reference voltages and soft values obtained from said flash memory device.

20. The integrated circuit of claim 16 , wherein said log likelihood ratio generation block is further configured to apply said log likelihood ratios to one or more of a soft decision decoder and a buffer.