Suspend SDRAM refresh cycles during normal DDR operation
View Patent ↗An apparatus comprising a test circuit and a protocol circuit. The test circuit may be configured to generate a plurality of control signals in response to one or more read data signals. The protocol circuit may be configured to generate a plurality of interface signals in response to the plurality of control signals. The protocol engine suspends a refresh operation during a normal operation of the apparatus.
1. An apparatus comprising:
a built in self test (BIST) engine configured to generate a plurality of control signals in response to one or more read data signals; and
a protocol engine configured to generate a plurality of interface signals in response to said plurality of control signals, wherein (A) said protocol engine suspends a refresh operation of a memory during a data integrity validation operation initiated by said built in self test engine, (B) said protocol engine comprises a state machine configured to switch between a plurality of states based upon a particular combination of requests received from said built in self test engine, and (C) a multiplexor circuit is configured to switch between (i) said apparatus and (ii) an external memory controller prior to addressing said memory.
2. The apparatus according to claim 1 , wherein said multiplexor (i) presents said plurality of control signals from said apparatus or a second plurality of control signals from said external memory controller and (ii) said switch occurs during a self refresh mode.
3. The apparatus according to claim 2 , wherein said plurality of states include an idle state, a command state, a pre-charge state, and a refresh state.
4. The apparatus according to claim 1 , wherein said apparatus is implemented as a controller of said memory.
5. The apparatus according to claim 4 , wherein (i) said memory comprises an SDRAM module and (ii) said interface signals are presented to said SDRAM module.
6. The apparatus according to claim 5 , wherein said SDRAM module comprises a double data rate (DDR) SDRAM.
7. The apparatus according to claim 1 , wherein said built in self test engine comprises a built-in self test (BIST) double data rate (DDR) circuit.
8. An apparatus comprising:
means for generating a plurality of control signals in response to one or more read data signals; and
means for generating a plurality of interface signals in response to said plurality of control signals, wherein (A) said apparatus suspends a refresh operation of a memory during a data integrity validation operation initiated by said apparatus, (B) said means for generating said interface signals switches between a plurality of states based upon a particular combination of requests received from said means for generating said control signals, and (C) a multiplexor is configured to switch between (i) said apparatus and (ii) an external memory controller prior to addressing said memory.
9. A method for implementing a controller in a memory, comprising the steps of:
(A) generating a plurality of control signals in response to one or more read data signals; and
(B) generating a plurality of interface signals in response to said plurality of control signals, wherein (a) said method suspends a refresh operation of said memory during a data integrity validation operation initiated by a built in self test engine, (b) step (B) includes implementing a state machine to switch between a plurality of states based upon a particular combination of requests received from step (B) and (c) switching between (i) said control with steps (A) and (B) and (ii) control using an external memory controller prior to addressing said memory.
10. The apparatus according to claim 1 , wherein said data integrity validation operation is performed during a normal operation of said apparatus.
11. The apparatus according to claim 1 , wherein said BIST engine and said protocol engine take control of generating auto refresh commands.
12. The apparatus according to claim 1 , wherein said data integrity validation operation comprises checkerboard, write/read address, data retention and march patterns of said memory.
13. The apparatus according to claim 1 , wherein said multiplexor selects between said apparatus and said memory controller during a self refresh mode.
14. The apparatus according to claim 13 , wherein a processor is connected to both said apparatus and said memory controller.
15. The apparatus according to claim 14 , wherein said processor is implemented as an ARM microprocessor.
16. The apparatus according to claim 14 , wherein said processor (i) configures a particular one of said data integrity validation operations to run, (ii) indicates when to start said data integrity validation operation, (iii) polls for completion of said data integrity validation operations and (iv) checks a result of said data integrity validation operation.
17. The apparatus according to claim 13 , wherein said multiplexor is further configured a receive a select signal configured to be acknowledged during a self-refresh mode of said memory.
18. The apparatus according to claim 1 , wherein said data validation operation is configured to check for errors on read operations and log results in a log register file.
19. The apparatus according to claim 8 , wherein said memory comprises an SDRAM.
20. The method according to claim 9 , wherein said memory comprises an SDRAM.