IP Library Granted Patent US 8,854,880
Granted Patent B2
US 8,854,880 · App. 13/778,860 · Granted Oct 7, 2014

Inter-cell interference cancellation in flash memories

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Quick Facts
Patent No.
US 8,854,880
App. No.
13/778,860
Granted
Oct 7, 2014
Kind
B2
Abstract

Inter-cell interference cancellation is provided for flash memory devices. Data from a flash memory device is processed by obtaining one or more quantized threshold voltage values for at least one target cell of the flash memory device; obtaining one or more hard decision read values for at least one aggressor cell of the target cell; determining an aggressor state of the at least one aggressor cell; determining an interference amount based on the aggressor state; determining an adjustment to the quantized threshold voltage values based on the determined interference amount; and adjusting the quantized threshold voltage values based on the determined adjustment. The quantized threshold voltage values for at least one target cell are optionally re-used from a previous soft read retry operation. The adjusted quantized threshold voltage values are optionally used to determine reliability values and are optionally applied to a soft decision decoder and/or a buffer.

Claims (33)

1. A method for processing data from a flash memory device, comprising:

obtaining one or more quantized threshold voltage values for at least one target cell of said flash memory device;

obtaining one or more hard decision read values for at least one aggressor cell of said target cell;

determining an aggressor state of said at least one aggressor cell;

determining an interference amount based on said aggressor state;

determining an adjustment to said one or more quantized threshold voltage values based on said determined interference amount; and

adjusting said one or more quantized threshold voltage values based on said determined adjustment.

2. The method of claim 1 , wherein said one or more quantized threshold voltage values for at least one target cell are re-used from a previous soft read retry operation.

3. The method of claim 1 , wherein said one or more quantized threshold voltage values comprises one or more of hard decision read values obtained by a plurality of read retries of said target cell at a plurality of reference voltages and soft values obtained from said flash memory device.

4. The method of claim 1 , further comprising the step of determining one or more reliability values based on said one or more adjusted quantized threshold voltage values.

5. The method of claim 4 , wherein one or more of said interference amount and said one or more reliability values are obtained from a look-up table.

6. The method of claim 1 , further comprising the step of applying said one or more adjusted quantized threshold voltage values to one or more of a soft decision decoder and a buffer.

7. The method of claim 1 , wherein said adjustment is set to zero if said one or more quantized threshold voltage values correspond to a trunk region of a threshold voltage distribution.

8. The method of claim 1 , wherein said adjustment is obtained by dividing said interference amount by a region size of a threshold voltage distribution.

9. The method of claim 1 , wherein said adjustment is obtained by quantizing said interference amount based on a width of one or more regions of a threshold voltage distribution.

10. The method of claim 1 , wherein said adjustment to said one or more quantized threshold voltage values is obtained from an inter-cell interference look-up table.

11. A tangible machine-readable recordable storage medium for processing data from a flash memory device, wherein one or more software programs when executed by one or more processing devices implement the steps of the method of claim 1 .

12. A flash memory system, comprising:

an intercell interference mitigation block configured to:

obtain one or more quantized threshold voltage values for at least one target cell of said flash memory device;

obtain one or more hard decision read values for at least one aggressor cell of said target cell;

determine an aggressor state of said at least one aggressor cell;

determine an interference amount based on said aggressor state;

determine an adjustment to said one or more quantized threshold voltage values based on said determined interference amount; and

adjust said one or more quantized threshold voltage values based on said determined adjustment.

13. The flash memory system of claim 12 , wherein said one or more quantized threshold voltage values for at least one target cell are re-used from a previous soft read retry operation.

14. The flash memory system of claim 12 , wherein said one or more quantized threshold voltage values comprises one or more of hard decision read values obtained by a plurality of read retries of said target cell at a plurality of reference voltages and soft values obtained from said flash memory device.

15. The flash memory system of claim 12 , wherein said intercell interference mitigation block is further configured to determine one or more reliability values based on said one or more adjusted quantized threshold voltage values.

16. The flash memory system of claim 15 , wherein one or more of said interference amount and said one or more reliability values are obtained from a look-up table.

17. The flash memory system of claim 12 , wherein said intercell interference mitigation block is further configured to apply said one or more adjusted quantized threshold voltage values to one or more of a soft decision decoder and a buffer.

18. The flash memory system of claim 12 , wherein said adjustment is obtained by dividing said interference amount by a region size of a threshold voltage distribution.

19. The flash memory system of claim 12 , wherein said adjustment is obtained by quantizing said interference amount based on a width of one or more regions of a threshold voltage distribution.

20. The flash memory system of claim 12 , wherein said adjustment to said one or more quantized threshold voltage values is obtained from an inter-cell interference look-up table.

Assignments (4)
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 21, 2015
From: LSI CORPORATION
To: SEAGATE TECHNOLOGY LLC
Reel/Frame 034775/0777 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 27, 2013
From: CHEN, ZHENGANG; HARATSCH, ERICH F.
To: LSI CORPORATION
Reel/Frame 029887/0192 →