Low pass filter circuit and voltage regulator
View Patent ↗Provided are a low pass filter circuit having a small output voltage shift caused by a substrate leakage current at high temperature, and a voltage regulator using the low pass filter circuit, which has a small output voltage shift at high temperature. In a low pass filter circuit using a PMOS transistor as a resistive element, a back gate terminal of the PMOS transistor is set to have a higher voltage than a source of the PMOS transistor. Further, in a voltage regulator incorporating the low pass filter circuit to an output of a reference voltage circuit, the voltage of the back gate terminal of the PMOS transistor which is higher than that of the source thereof is generated by the reference voltage circuit.
1. A low pass filter circuit comprising:
a first PMOS transistor;
a second PMOS transistor;
a capacitor;
a back gate voltage source connected between a back gate terminal and an input terminal of the low pass filter circuit; and
a current source,
the first PMOS transistor including a source connected to the input terminal, a drain connected to an output terminal of the low pass filter circuit, and a gate connected to one terminal of the current source,
the second PMOS transistor including a source connected to the input terminal, and a gate and a drain connected to the one terminal of the current source,
the capacitor being connected between the output terminal and a ground terminal,
the current source having another terminal grounded,
the first PMOS transistor and the second PMOS transistor connected to the back gate terminal and having the same substrate potential which is higher than a source potential of the first PMOS transistor and the second PMOS transistor,
wherein a voltage at the back gate terminal is higher than that of the ground terminal by a predetermined amount.
2. A voltage regulator comprising:
a reference voltage generation circuit;
an amplifier;
an output transistor; and
the low pass filter circuit according to claim 1 ,
the reference voltage generation circuit including the back gate voltage source and configured to generate a first reference voltage and a second reference voltage higher than the first reference voltage,
the low pass filter circuit including the input terminal to which the first reference voltage is input, and the output terminal connected to a first input terminal of the amplifier,
the output transistor including a gate connected to an output terminal of the amplifier, a source connected to a power source, and a drain connected to an output terminal of the voltage regulator and to a second input terminal of the amplifier,
the second reference voltage being connected to a substrate of each of the first PMOS transistor and the second PMOS transistor.
3. A voltage regulator according to claim 2 , wherein the reference voltage generation circuit includes a plurality of resistors connected in series, and wherein one of the plurality of resistors comprises the back gate voltage source and the first reference voltage and the second reference voltage are output from the plurality of resistors.
4. A voltage regulator according to claim 2 ,
wherein the reference voltage generation circuit further comprises:
a first NMOS depletion transistor, a second NMOS depletion transistor, and an NMOS enhancement transistor, each having gates connected in common,
wherein the first NMOS depletion transistor includes a drain connected to the power source and a source connected to a drain of the second NMOS depletion transistor
the second NMOS depletion transistor includes a gate and a source connected to a gate and a drain of the NMOS enhancement transistor,
the NMOS enhancement transistor includes a source grounded, and
the first reference voltage is output from the drain of the NMOS enhancement transistor, and the second reference voltage is output from the drain of the second NMOS depletion transistor and comprising the back gate voltage source.