Intelligent context management
View Patent ↗Intelligent context management for thread switching is achieved by determining that a register bank has not been used by a thread for a predetermined number of dispatches, and responsively disabling the register bank for use by that thread. A counter is incremented each time the thread is dispatched but the register bank goes unused. Usage or non-usage of the register bank is inferred by comparing a previous checksum for the register bank to a current checksum. If the previous and current checksums match, the system concludes that the register bank has not been used. If a thread attempts to access a disabled bank, the processor takes an interrupt, enables the bank, and resets the corresponding counter. For a system utilizing transactional memory, it is preferable to enable all of the register banks when thread processing begins to avoid aborted transactions from register banks disabled by lazy context management techniques.
1. A method of intelligent context management for thread switching in a processing unit having execution units and register banks used by the execution units, the method comprising:
determining that a given register bank has not been used by a particular thread for a predetermined number of dispatches of the particular thread; and
responsive to said determining, disabling the given register bank for use by the particular thread while still enabling the given register bank for at least one other thread, wherein disabling of said given register bank includes not restoring a context of said given register bank for a dispatch of the particular thread and includes not saving the context of said given register bank when the particular thread is switched out of the processor core.
2. The method of claim 1 wherein said determining includes:
inferring after a current dispatch of the particular thread that the particular thread has not used the given register bank since a previous dispatch of the particular thread; and
responsive to said inferring, incrementing a counter corresponding to the particular thread and the given register bank beyond a predetermined threshold.
3. The method of claim 2 wherein said inferring includes:
storing a previous checksum for a state of the given register bank from the previous dispatch; and
establishing that a current checksum for a state of the given register bank from the current dispatch is equal to the previous checksum.
4. The method of claim 1 wherein said determining and said disabling are controlled by operating system software of a computer system which includes the processing unit.
5. The method of claim 1 wherein processing of the particular thread begins with all of the register banks enabled.
6. The method of claim 1 wherein:
the register banks include general purpose registers, floating point registers, vector registers, and vector-scalar registers; and
said disabling selectively disables one of said floating point registers, said vector registers, and said vector-scalar registers.
7. The method of claim 3 further comprising, prior to said determining and said disabling:
storing a last saved checksum for the state of the given register bank;
switching out a thread context of the processing unit after said storing;
confirming that a new checksum for the state of the given register bank after said switching does not match the last saved checksum; and
responsive to said confirming, resetting the counter to zero.
8. A method of intelligent context management for thread switching in a processing unit having execution units and register banks used by the execution units, the method comprising:
determining that a given register bank has not been used by a particular thread for a predetermined number of dispatches of the particular thread, wherein the predetermined number is programmable and is dynamically set based on the particular thread's usage of said given register bank in real time; and
responsive to said determining, disabling the given register bank for use by the particular thread.
9. The method of claim 8 wherein the predetermined number is set accordingly to a number of dispatches that occur between successive uses of a particular one of the execution units by the particular thread.