Systems and Methods for Signal Reduction Based Data Processor Marginalization

1 . A data processing system, the data processing system comprising:

a signal modification circuit operable to:

filter a data set to yield a signal component;

multiply the signal component by a scalar to yield a product;

subtract the product from a data input to yield a signal modified output, wherein the data set is derived from the data input; and

select one of the data set and the signal modified output as a processing input; and

a processing circuit operable to apply a data processing algorithm to the processing input to yield a data output.

2 . The data processing system of claim 1 , wherein the scalar is programmable.

3 . The data processing system of claim 2 , wherein the scalar is programmed with a value less than unity that is large enough to decrease a signal to noise ratio of the signal modified output when compared with a signal to noise ratio of the data set.

4 . The data processing system of claim 2 , wherein the scalar is programmed with a value less than unity that is small enough to increase a reliability of the signal modified output when compared with the data set.

5 . The data processing system of claim 1 , wherein the data processing system further comprises:

an equalizer circuit operable to equalize a sample set to yield the data input; and

a data detector circuit operable to apply a data detection algorithm to the data input to yield the data set.

6 . The data processing system of claim 5 , wherein the resolution of the data input is greater than the resolution of the processing input.

7 . The data processing system of claim 6 , wherein the resolution of the data input is thirteen bits, and wherein the resolution of the processing input is six bits.

8 . The data processing system of claim 5 , wherein the resolution of the signal component is greater than the resolution of the processing input.

9 . The data processing system of claim 1 , wherein the signal modification circuit comprises:

a partial response target filter circuit operable to filter the data set to yield the signal component;

a multiplier circuit operable to multiply the signal component by the scalar to yield the product; and

summation circuit operable to subtract the product from the data input to yield the signal modified output.

10 . The data processing system of claim 1 , wherein the scalar is less than unity.

11 . The data processing system of claim 1 , wherein the processing circuit comprises:

a data detector circuit operable to apply a data detection algorithm to the processing input to yield a detected output; and

a data decoder circuit operable to apply a data decoding algorithm to a decoder input derived from the detected output to yield the data output.

12 . The data processing system of claim 11 , wherein the data decoder circuit is a low density parity check decoder circuit.

13 . The data processing system of claim 11 , wherein the data detector circuit is selected from a group consisting of: a maximum a posteriori data detector circuit, and a Viterbi algorithm data detector circuit.

14 . The data processing system of claim 1 , wherein the system is implemented as an integrated circuit.

15 . The data processing system of claim 1 , wherein the data processing system is implemented as part of a device selected from a group consisting of: a storage device, and a communication device.

16 . A method for data processing, the method comprising:

receiving a data set;

equalizing the data set to yield a data input;

generating a signal component based at least in part on a second detected output derived from the data input;

multiplying the signal component by a scalar to yield a product;

subtracting the product from the data input to yield a signal modified output;

selecting one of the data input and the signal modified output as a processing input;

applying a data detection algorithm to the processing input to yield a first detected output.

17 . The method of claim 16 , wherein the scalar is programmable, and wherein the method further comprises:

programming the scalar with a value less than unity that is large enough to decrease a signal to noise ratio of the signal modified output when compared with a signal to noise ratio of the data input.

18 . The method of claim 16 , wherein the scalar is programmable, and wherein the method further comprises:

programming the scalar with a value less than unity that is small enough to increase a reliability of the signal modified output when compared with the data set.

19 . The method of claim 16 , wherein the data detection algorithm is a first data detection algorithm, and wherein the method further comprises:

applying a second data detection algorithm to the data input to yield the second detected output.

20 . A storage device, the storage device comprising:

a storage medium;

a head assembly disposed in relation to the storage medium and operable to provide a sensed signal corresponding to a data set on the storage;

a read channel circuit including:

an analog front end circuit operable to provide an analog signal corresponding to the sensed signal;

an analog to digital converter circuit operable to sample the analog signal to yield a series of digital samples;

an equalizer circuit operable to equalize the digital samples corresponding to the data set to yield a data set;

a loop detector circuit operable to apply a loop detection algorithm to the data set to yield a detected output;

a signal modification circuit operable to:

filter the detected output to yield a signal component;

multiply the signal component by a scalar to yield a product;

subtract the product from a data set to yield a signal modified output, wherein the data set is derived from the data input;

select one of the data set and the signal modified output as a processing input; and

a processing circuit operable to apply a data processing algorithm to the processing input to yield a data output.