IP Library Granted Patent US 9,590,078
Granted Patent B2
US 9,590,078 · App. 13/784,662 · Granted Mar 7, 2017

Semiconductor device fabrication method and semiconductor device

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Quick Facts
Patent No.
US 9,590,078
App. No.
13/784,662
Granted
Mar 7, 2017
Kind
B2
Abstract

A semiconductor device fabrication method includes forming a tunnel insulating film on a substrate containing silicon, forming a floating gate on the tunnel insulating film, forming an integral insulating film on the floating gate, and forming a control gate on the integral insulating film. The floating gate is formed on the tunnel insulating film by forming a seed layer containing amorphous silicon on the tunnel insulating film, forming an impurity later containing adsorbed boron or germanium on the seed layer, and forming a cap layer containing silicon on the impurity layer.

Claims (36)

1. A semiconductor device fabrication method comprising:

forming a tunnel insulating film on a substrate containing silicon;

forming a floating gate on the tunnel insulating film;

forming a gate insulating film on the floating gate; and

forming a control gate on the gate insulating film,

wherein said forming the floating gate includes forming a seed layer containing amorphous silicon on the tunnel insulating film, forming an impurity layer containing boron on the seed layer, and forming a cap layer containing silicon on the impurity layer that contains boron, the impurity layer containing boron before the cap layer is formed, and

wherein said forming the floating gate further includes forming a region in which chlorine is adsorbed on the seed layer and the impurity layer is formed on the region in which chlorine is adsorbed on the seed layer.

2. The method according to claim 1 , wherein said forming the floating gate further includes forming an adjustment layer containing silicon.

3. The method according to claim 1 , wherein said forming the floating gate further includes forming an adjustment layer containing silicon between the seed layer and the impurity layer.

4. The method according to claim 1 , wherein the cap layer contains amorphous silicon.

5. The method according to claim 1 , wherein a temperature under which the seed layer is formed is in a range of 400° C. to 420° C.

6. The method according to claim 5 , wherein a temperature under which the impurity layer is formed is in a range of 400° C. to 420° C.

7. The method according to claim 6 , wherein a temperature under which the cap layer is formed is in a range of 400° C. to 420° C.

8. The method according to claim 7 , wherein the seed layer, impurity layer, and the cap layers are formed in a same chamber.

9. The method according to claim 1 , wherein said forming the floating gate further includes conducting a post-oxidizing treatment under a temperature of about 800° C.

10. A method for fabricating a semiconductor device having a film formed by doping at least boron or germanium into silicon, the method comprising:

forming a seed layer containing amorphous silicon;

forming a region in which chlorine is adsorbed on the seed layer;

forming an impurity layer containing at least boron or germanium on the region in which chlorine is adsorbed on the seed layer; and

forming a cap layer containing silicon on the impurity layer that contains boron or germanium, the impurity layer containing boron or germanium before the cap layer is formed.

11. The method according to claim 10 , further comprising:

forming an adjustment layer containing silicon between the seed layer and the impurity layer.

12. The method according to claim 10 , further comprising:

forming an adjustment layer containing silicon on the cap layer.

13. The method according to claim 10 , wherein the cap layer contains amorphous silicon.

14. The method according to claim 10 , wherein a temperature under which the seed layer is formed is in a range of 400° C. to 420° C.

15. The method according to claim 14 , wherein a temperature under which the impurity layer is formed is in a range of 400° C. to 420° C.

16. The method according to claim 15 , wherein a temperature under which the cap layer is formed is in a range of 400° C. to 420° C.

17. The method according to claim 16 , wherein the seed layer, impurity layer, and the cap layer are formed in a same chamber.

18. A semiconductor device fabrication method comprising:

forming a tunnel insulating film on a substrate containing silicon;

forming a floating gate on the tunnel insulating film;

forming a gate insulating film on the floating gate; and

forming a control gate on the gate insulating film,

wherein said forming the floating gate includes forming a seed layer containing amorphous silicon on the tunnel insulating film, forming an impurity layer containing boron on the seed layer, and forming a cap layer containing silicon on the impurity layer that contains boron, the impurity layer containing boron before the cap layer is formed, and

wherein forming the impurity layer containing boron comprises thermally decomposing a boron compound and adsorbing boron from a gas phase on the seed layer.

Assignments (5)
MERGER Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: K.K. PANGEA
Reel/Frame 055659/0471 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: TOSHIBA MEMORY CORPORATION
To: KIOXIA CORPORATION
Reel/Frame 055669/0001 →
CHANGE OF NAME AND ADDRESS Recorded Jan 22, 2021
From: K.K. PANGEA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 055669/0401 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 14, 2017
From: KABUSHIKI KAISHA TOSHIBA
To: TOSHIBA MEMORY CORPORATION
Reel/Frame 043194/0647 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 9, 2013
From: ISHIDA, HIROKAZU; TORATANI, KENICHIRO
To: KABUSHIKI KAISHA TOSHIBA
Reel/Frame 030762/0204 →