IP Library Granted Patent US 9,454,474
Granted Patent B2
US 9,454,474 · App. 13/786,352 · Granted Sep 27, 2016

Methods, devices and systems for two stage power-on map rebuild with free space accounting in a solid state drive

View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 9,454,474
App. No.
13/786,352
Granted
Sep 27, 2016
Kind
B2
Abstract

A data storage device comprises a non-volatile memory comprising a plurality of blocks, each configured to store a plurality of physical pages at predetermined physical locations. A controller programs and reads data stored in a plurality of logical pages. A volatile memory comprises a logical-to-physical address translation map configured to enabling determination of the physical location, within one or more physical pages, of the data stored in each logical page. A plurality of journals may be stored, each comprising a plurality of entries associating one or more physical pages to each logical page. At startup, the controller may read at least some of the plurality of journals in an order and rebuild the map; indicate a readiness to service data access commands after the map is rebuilt; rebuild a table from the map and, based thereon, select block(s) for garbage collection after having indicated the readiness to process the commands.

Claims (34)

1. A data storage device controller configured to couple to a non-volatile memory comprising a plurality of blocks, each block being configured to store a plurality of physical pages at predetermined physical locations, the controller comprising:

a processor configured to program data to and read data from the non-volatile memory, the data being stored in a plurality of logical pages;

a volatile memory comprising a logical-to-physical address translation map configured to enable the processor to determine a physical location, within one or more physical pages, of the data stored in each logical page; and

a plurality of journals stored in the non-volatile memory, each journal corresponding to at least one of the plurality of blocks and comprising a plurality of journal entries associating one or more physical pages to each logical page, wherein each of the plurality of journals covers a pre-determined range of physical pages within one of the plurality of blocks,

wherein the controller is configured, upon startup, to:

read each of the plurality of journals in an order and to rebuild the map in the volatile memory from the read of each of the plurality of journals;

indicate a readiness to process data access commands after the map is rebuilt;

rebuild a table from the map and select, based on the rebuilt table, at least one of the plurality of blocks for garbage collection after having indicated the readiness to process data access commands;

locate a corresponding journal for the selected block to determine whether any entries in the corresponding journal point to valid data on the selected block;

relocate all of the valid data, as indicated by the corresponding journal, from the selected block to another block in the non-volatile memory; and

generate a new journal for the block storing the valid data.

2. The data storage device controller of claim 1 , wherein the processor is further configured to build a journal map in the volatile memory as each of the plurality of journals is read, the journal map specifying a physical location in the non-volatile memory of each of the read journals.

3. The data storage device controller of claim 1 , wherein the non-volatile memory comprises Multi-Level Cells (MLC) and wherein the processor is further configured to store each logical page in a non-volatile buffer at least until an upper page corresponding to a lower page of non-volatile memory where the logical page is stored has been programmed.

4. The data storage device controller of claim 3 , wherein the processor is further configured to read logical pages stored in the non-volatile buffer and to rebuild the map using the logical pages read from the non-volatile buffer.

5. The data storage device controller of claim 1 , wherein the non-volatile memory comprises Multi-Level Cells (MLC), wherein the non-volatile memory comprises a physical area comprising recently garbage-collected valid logical pages and wherein the processor is further configured to read journals corresponding to the physical area no further than entries thereof corresponding to safe logical pages stored in a lower page of non-volatile memory where the corresponding upper page has been programmed.

6. The data storage device controller of claim 5 , wherein, for entries of journals corresponding to the physical area corresponding to unsafe logical pages stored in a lower page where the corresponding upper page has not been programmed, the processor is further configured to read journals associating one or more physical pages of a block from which the valid data was garbage collected.

7. A data storage device, comprising:

the non-volatile memory, and

the data storage device controller of claim 1 .

8. A method of controlling a data storage device comprising a non-volatile memory comprising a plurality of blocks, each block being configured to store a plurality of physical pages at predetermined physical locations, the method comprising:

programming data to and reading data from the non-volatile memory, the data being stored in a plurality of logical pages;

maintaining, in a volatile memory, a logical-to-physical address translation map configured to enable a determination of a physical location, within one or more physical pages, of the data stored in each logical page; and

maintaining, in the non-volatile memory, a plurality of journals, each journal corresponding to at least one of the plurality of blocks and comprising a plurality of journal entries associating one or more physical pages to each logical page, wherein each of the plurality of journals covers a pre-determined range of physical pages within one of the plurality of blocks and, upon startup:

reading each of the plurality of journals in an order and rebuilding the map in the volatile memory from the read of each of the plurality of journals;

indicating a readiness to process data access commands after the map is rebuilt; and

rebuilding a table from the map and, based on the rebuilt table, selecting at least one of the plurality of blocks for garbage collection after having indicated the readiness to process data access commands;

locating a corresponding journal for the selected block to determine whether any entries in the corresponding journal point to valid data on the selected block;

relocating all of the valid data, as indicated by the corresponding journal, from the selected block to another block in the non-volatile memory; and

generating a new journal for the block storing the valid data.

9. The method of claim 8 , further comprising building a journal map in the volatile memory as each of the plurality of journals is read, the journal map specifying a physical location in the non-volatile memory of each of the read journals.

10. The method of claim 8 , wherein the non-volatile memory comprises Multi-Level Cells (MLC) and wherein the method further comprises storing each logical page in a non-volatile buffer at least until an upper page corresponding to a lower page of non-volatile memory where the logical page is stored has been programmed.

11. The method of claim 10 , further comprising reading logical pages stored in the non-volatile buffer and rebuilding the map using the logical pages read from the non-volatile buffer.

12. The method of claim 8 , wherein the non-volatile memory comprises Multi-Level Cells (MLC), wherein the non-volatile memory comprises a physical area of memory storing data retained from a garbage collection process and wherein the method further comprises reading journals corresponding to the physical area no further than entries thereof corresponding to safe logical pages stored in a lower page of non-volatile memory where the corresponding upper page has been programmed.

13. The method of claim 12 wherein, for entries of journals corresponding to the physical area corresponding to unsafe logical pages stored in a lower page where the corresponding upper page has not been programmed, the method further comprises reading journals associating one or more physical pages of a block from which the valid data was garbage collected.

Assignments (11)
PATENT COLLATERAL AGREEMENT - DDTL LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 067045/0156 →
PATENT COLLATERAL AGREEMENT - A&R LOAN AGREEMENT Recorded Aug 21, 2023
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A.
Reel/Frame 064715/0001 →
RELEASE OF SECURITY INTEREST AT REEL 038744 FRAME 0481 Recorded Feb 8, 2022
From: JPMORGAN CHASE BANK, N.A.
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 058982/0556 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded May 29, 2018
From: SKYERA, LLC
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 046726/0328 →
RELEASE OF SECURITY INTEREST Recorded Mar 5, 2018
From: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
To: WESTERN DIGITAL TECHNOLOGIES, INC.
Reel/Frame 045501/0714 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038722/0229 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: U.S. BANK NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 038744/0281 →
SECURITY AGREEMENT Recorded May 17, 2016
From: WESTERN DIGITAL TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 038744/0481 →
CHANGE OF NAME Recorded Jul 17, 2015
From: SKYERA, INC.
To: SKYERA, LLC
Reel/Frame 036129/0673 →
RELEASE OF SECURITY INTEREST Recorded Jan 6, 2015
From: DELL PRODUCTS L.P.
To: SKYERA, LLC
Reel/Frame 034742/0069 →
SECURITY INTEREST Recorded Nov 11, 2014
From: SKYERA, INC.
To: WESTERN DIGITAL CAPITAL, INC.
Reel/Frame 034204/0849 →