Nonvolatile semiconductor memory device
View Patent ↗A nonvolatile semiconductor memory device includes an array of memory cells arranged at the position intersecting positions of the word line and the bit line, a control signal generating circuit for carrying out a writing operation including a program for carrying out writing in the memory cell and a verification for verifying whether the data has been correctly written in the memory cell by the program, and a cell source monitoring circuit for detecting a voltage of the source line connected to the memory cell during the writing operation. The control signal generating circuit directly shifts the source line voltage at the time of program to a lower voltage necessary at the time of verification after the end of the program, based on the voltage the source line detected by the cell source monitoring circuit.
1. A nonvolatile semiconductor memory device, comprising:
a memory cell array having a plurality of memory cells arranged at intersections of word lines and bit lines;
a control circuit configured to carry out a write operation including a program for carrying out writing data to a memory cell, and verification for verifying whether the data has been correctly written to the memory cell by the program; and
a source line monitoring circuit configured to detect a voltage of a source line connected to the memory cell during the write operation,
wherein the control circuit is configured to directly shift the voltage of the source line, without first discharging the source line, from a first voltage equal to a voltage of the source line during the program to a second voltage equal to a voltage required at the time of verification after the end of the program.
2. The nonvolatile semiconductor memory device according to claim 1 , wherein the control circuit is configured to directly shift the voltage of the source line from the first voltage to the second voltage based on the voltage of the source line detected by the source line monitoring circuit.
3. The nonvolatile semiconductor memory device according to claim 2 , wherein the control circuit is configured to directly shift the voltage of the source line from the first voltage to the second voltage when the voltage of the source line detected by the source line monitoring circuit after the end of the program is the first voltage.
4. The nonvolatile semiconductor memory device according to claim 1 , further comprising:
a word line monitoring circuit configured to detect a voltage of the word line during the write operation,
wherein the control circuit is further configured to directly shift a voltage of a selected word line to a third voltage, and directly shift a voltage of a nonselected word line to a fourth voltage, based on the voltage of the word line detected by the word line monitoring circuit.
5. The nonvolatile semiconductor memory device according to claim 4 , wherein the control circuit is configured to directly shift a voltage of a gate line of a select transistor connected to the memory cell from a fifth voltage that has been set during the program to a sixth voltage required at the time of verification after the end of the program.
6. The nonvolatile semiconductor memory device according to claim 1 , wherein the control circuit is configured to shift the voltage of the source line from the first voltage to the second voltage without the source line being discharged to a voltage lower than the second voltage.
7. The nonvolatile semiconductor memory device according to claim 1 , wherein the memory cell array includes memory cells connected in series, and a cell unit including a select transistor connected to both ends of the memory cells, and wherein the source line is connected to one end of the cell unit.
8. A nonvolatile semiconductor memory device, comprising:
a memory cell array having a plurality of memory cells arranged at intersections of word lines and bit lines;
a control circuit configured to carry out a write operation including a program for carrying out writing data to a memory cell, and verification for verifying whether the data has been correctly written to the memory cell by the program;
a source line monitoring circuit configured to detect a voltage of a source line connected to the memory cell during the write operation; and
a word line monitoring circuit configured to detect a voltage of the word line during the write operation,
wherein the control circuit is configured to directly shift each voltage of the source line and a selected word line from a high level to a low level without discharging either the source line or the selected word line to a level that is lower than the low level.
9. The nonvolatile semiconductor memory device according to claim 8 , wherein the control circuit is configured to directly shift each voltage of the source line and the selected word line from a high level to a low level without discharging either the source line or the selected word line to a ground reference voltage.
10. The nonvolatile semiconductor memory device according to claim 8 , wherein the control circuit is configured to directly shift the voltage of the source line based on the voltage of the source line detected by the source line monitoring circuit and the voltage of the selected word line based on the voltage of the word line detected by the word line monitoring circuit.
11. The nonvolatile semiconductor memory device according to claim 8 , wherein the memory cell array includes memory cells connected in series, and a cell unit including a select transistor connected to both ends of the memory cells, and wherein the source line is connected to one end of the cell unit.
12. The nonvolatile semiconductor memory device according to claim 8 , wherein the control circuit is configured to directly shift a voltage of a gate line of a select transistor connected to the memory cell between two levels at the time of verification after the end of the program.
13. The nonvolatile semiconductor memory device according to claim 12 , wherein the lower of the two levels is greater than zero.
14. A method of writing data to a nonvolatile semiconductor memory device having a memory cell array having a plurality of memory cells arranged at intersections of word lines and bit lines, said method comprising:
writing data to a memory cell according to a program during a writing operation;
after the end of the program, directly shifting a voltage of a source line connected to the memory cell, without first discharging the source line, from a first voltage equal to a voltage of the source line during the program to a second voltage equal to a voltage of the source line required at the time of verification of data written to the memory cell; and
verifying whether the data has been correctly written to the memory cell.
15. The method according to claim 14 , further comprising:
detecting a source line voltage at the source line,
wherein the voltage of the source line is directly shifted from the first voltage to the second voltage based on the detected source line voltage.
16. The method according to claim 15 , wherein the voltage of the source line is directly shifted from the first voltage to the second voltage when the voltage of the source line detected by the source line monitoring circuit after the end of the program is the first voltage.
17. The method according to claim 14 , further comprising:
directly shifting a voltage of a selected word line to a third voltage after the end of the program; and
directly shifting a voltage of a nonselected word line to a fourth voltage after the end of the program.
18. The method according to claim 17 , further comprising:
detecting a word line voltage at the selected word line,
wherein the voltages of the selected and nonselected word lines are directly shifted based on the detected word line voltage.
19. The method according to claim 17 , further comprising:
after the end of the program, directly shifting a voltage of a gate line of a select transistor connected to the memory cell from a fifth voltage that has been set during the program to a sixth voltage required at the time of verification.