Data storage device increasing sequence detector clock frequency when bottleneck condition is detected
View Patent ↗A data storage device is disclosed comprising a non-volatile memory (NVM). During a read operation, a sequence of signal samples is generated representing codewords stored in the NVM. The signal samples are buffered to generate buffered signal samples. The buffered signal samples are processed at a first frequency to detect a data sequence, and a bottleneck condition is detected associated with processing the buffered signal samples at the first frequency. When the bottleneck condition is detected, the buffered signal samples are processed at a second frequency higher than the first frequency to detect the data sequence.
1. A data storage device comprising:
a non-volatile memory (NVM); and
control circuitry operable to:
during a read operation, generate a sequence of signal samples representing codewords stored in the NVM;
buffer the signal samples to generate buffered signal samples;
process the buffered signal samples at a first frequency to detect a data sequence;
detect a bottleneck condition associated with processing the buffered signal samples at the first frequency; and
when the bottleneck condition is detected, process the buffered signal samples at a second frequency higher than the first frequency to detect the data sequence.
2. The data storage device as recited in claim 1 , wherein the control circuitry is operable to generate the sequence of signal samples at the first frequency.
3. The data storage device as recited in claim 2 , wherein the control circuitry is further operable to buffer the signal samples in a buffer at the first frequency.
4. The data storage device as recited in claim 3 , wherein the control circuitry is operable to buffer the signal samples of a first codeword in the buffer at the first frequency and concurrently process the buffered signal samples of a second codeword at the second frequency to detect the data sequence.
5. The data storage device as recited in claim 1 , wherein the control circuitry is operable to:
transfer the buffered signal samples from the buffer to a sequence detector at the first frequency; and
when the bottleneck condition is detected, transfer the buffered signal samples from the buffer to the sequence detector at the second frequency.
6. The data storage device as recited in claim 1 , wherein the control circuitry is operable to detect the bottleneck condition when the buffered signal samples exceed a threshold.
7. The data storage device as recited in claim 1 , wherein the control circuitry is operable to detect the bottleneck condition when a number of codewords represented by the buffered signal samples exceeds a threshold.
8. The data storage device as recited in claim 1 , wherein the control circuitry is operable to detect the bottleneck condition when a time to process a plurality of the buffered signal samples representing one of the codewords exceeds a threshold.
9. The data storage device as recited in claim 8 , wherein the control circuitry is operable to:
process the plurality of the buffered signal samples using an iterative sequence detector over a number of iterations; and
detect the bottleneck condition when the number of iterations exceeds a threshold.
10. The data storage device as recited in claim 1 , wherein the NVM comprises a non-volatile semiconductor memory.
11. The data storage device as recited in claim 1 , wherein the NVM comprises a disk of a disk drive.
12. A method of operating a data storage device comprising a non-volatile memory (NVM), the method comprising:
during a read operation, generating a sequence of signal samples representing codewords stored in the NVM;
buffering the signal samples to generate buffered signal samples;
processing the buffered signal samples at a first frequency to detect a data sequence;
detecting a bottleneck condition associated with processing the buffered signal samples at the first frequency; and
when the bottleneck condition is detected, processing the buffered signal samples at a second frequency higher than the first frequency to detect the data sequence.
13. The method as recited in claim 12 , further comprising generating the sequence of signal samples at the first frequency.
14. The method as recited in claim 13 , further comprising buffering the signal samples in a buffer at the first frequency.
15. The method as recited in claim 14 , further comprising buffering the signal samples of a first codeword in the buffer at the first frequency and concurrently processing the buffered signal samples of a second codeword at the second frequency to detect the data sequence.
16. The method as recited in claim 12 , further comprising:
transferring the buffered signal samples from the buffer to a sequence detector at the first frequency; and
when the bottleneck condition is detected, transferring the buffered signal samples from the buffer to the sequence detector at the second frequency.
17. The method as recited in claim 12 , further comprising detecting the bottleneck condition when the buffered signal samples exceed a threshold.
18. The method as recited in claim 12 , further comprising detecting the bottleneck condition when a number of codewords represented by the buffered signal samples exceeds a threshold.
19. The method as recited in claim 12 , further comprising detecting the bottleneck condition when a time to process a plurality of the buffered signal samples representing one of the codewords exceeds a threshold.
20. The method as recited in claim 19 , further comprising:
processing the plurality of the buffered signal samples using an iterative sequence detector over a number of iterations; and
detecting the bottleneck condition when the number of iterations exceeds a threshold.
21. The method as recited in claim 12 , wherein the NVM comprises a non-volatile semiconductor memory.
22. The method as recited in claim 12 , wherein the NVM comprises a disk of a disk drive.