Non-volatile semiconductor memory
View Patent ↗A non-volatile semiconductor memory includes a word line extending in a first direction, a first electrode connected to the word line electrically, an ion diffusion layer with connected to the first electrode electrically, a second electrode connected to the ion diffusion layer electrically and formed of a metal to be diffused into the ion diffusion layer when a positive voltage is supplied thereto, and a bit line extending in a second direction perpendicular to the first direction, the bit line connected to the second electrode electrically. The ion diffusion layer has a first region disposed on the first electrode and a second region disposed between the first region and the second electrode, and the metal is more difficult to diffuse into the second region than into the first region.
1. A non-volatile semiconductor memory comprising:
a word line extending in a first direction;
a first electrode connected to the word line electrically;
an ion diffusion layer with connected to the first electrode electrically;
a second electrode connected to the ion diffusion layer electrically and formed of a metal to be diffused into the ion diffusion layer when a positive voltage is supplied thereto; and
a bit line extending in a second direction perpendicular to the first direction, the bit line connected to the second electrode electrically,
the ion diffusion layer having a first region disposed on the first electrode and a second region disposed between the first region and the second electrode, the metal being more difficult to diffuse into the second region than into the first region.
2. The non-volatile semiconductor memory according to claim 1 , wherein the second region has a higher concentration of impurities than the first region.
3. The non-volatile semiconductor memory according to claim 2 , wherein the impurity contains at least one element selected from oxygen, nitrogen, and carbon.
4. The non-volatile semiconductor memory according to claim 2 , wherein the first region is a substantially non-doped.
5. The non-volatile semiconductor memory according to claim 2 , wherein the ion diffusion layer has a third region disposed between the second electrode and the second region, the third region having a lower concentration of impurities than the second region.
6. The non-volatile semiconductor memory according to claim 5 , wherein the third region has protuberant parts at an interface between the second electrode and the third region.
7. The non-volatile semiconductor memory according to claim 5 , wherein the third region is formed separately and arranged in parallel on the surface of the second region.
8. The non-volatile semiconductor memory according to claim 6 , wherein the third region contains chlorine.
9. The non-volatile semiconductor memory according to claim 1 , wherein the second electrode is formed of at least one element selected from Ag, Cu, Al, Co, Ni, and Ti.
10. The non-volatile semiconductor memory according to claim 1 , wherein the first electrode is formed of an n-type polysilicon.
11. The non-volatile semiconductor memory according to claim 10 , wherein the first electrode contains n-type impurities with a concentration 1×10 18 /cm 3 or more.
12. The non-volatile semiconductor memory according to claim 1 , wherein a concentration of impurities in the first region is 1×10 20 /cm 3 or less.
13. The non-volatile semiconductor memory according to claim 1 , wherein a concentration of impurities in the second region is 2×10 20 /cm 3 or more.
14. The non-volatile semiconductor memory according to claim 1 , wherein the ion diffusion layer is formed of amorphous silicon.
15. The non-volatile semiconductor memory according to claim 1 , further comprising:
a second word line extending along the first direction;
a third electrode connected to the second word line electrically;
a second ion diffusion layer connected to the third electrode layer electrically; and
a fourth electrode connected to the second ion diffusion layer and the bit line electrically and formed of a metal to be diffused into the second ion diffusion layer when a positive voltage is applied to the fourth electrode,
the second ion diffusion layer having a fourth region disposed on the third electrode and a fifth region disposed between the fourth region and the fourth electrode, the metal being more difficult to diffuse into the fifth region than into the fourth region.
16. The non-volatile semiconductor memory according to claim 15 , wherein the fifth region has a higher concentration of impurities than the fourth region.
17. The non-volatile semiconductor memory according to claim 16 , wherein the second ion diffusion layer has a sixth region disposed between the fourth electrode and the fifth region, the sixth region having a lower concentration of impurities than the fifth region.
18. The non-volatile semiconductor memory according to claim 15 , wherein the third electrode is formed of an n-type polysilicon.
19. The non-volatile semiconductor memory according to claim 15 , wherein a concentration of impurities in the fourth region is 1×10 20 /cm 3 or less.
20. The non-volatile semiconductor memory according to claim 15 , wherein a concentration of impurities in the fifth region is 2×10 20 /cm 3 or more.