Low drop out voltage regulator

1. A low drop out voltage regulator comprising:

a transistor having an input node, an output node, and a control node; a differential amplifier having an output connected to the control node of the transistor and having a first input node; and

a feedback capacitor connected between the output node of the transistor and the first input of the differential amplifier, wherein a voltage at the output of the transistor is dependent on a charge across the feedback capacitor.

2. A low drop out voltage regulator according to claim 1 , further comprising a switched capacitor divider network having an input connected to the output node of the transistor and an output connected to feedback capacitor.

3. A low drop out voltage regulator according to claim 2 , wherein the switched capacitor divider network is periodically operational to apply charge to the feedback capacitor.

4. A low drop out voltage regulator according to claim 3 , wherein the switched capacitor divider network includes first and second capacitors connected in parallel and a plurality of controllable switches.

5. A low drop out voltage regulator according to claim 4 , wherein during a first phase of operation the plurality of switches are configured to couple the first capacitor between the output node of the transistor and ground, and to couple both terminals of the second capacitor to ground.

6. A low drop out voltage regulator according to claim 5 , wherein during a second phase of operation the plurality of switches are configured to couple the first capacitor in parallel with the second capacitor.

7. A low drop out voltage regulator according to claim 6 , wherein during a third phase of operation the plurality of switches are configured to couple the first and second capacitors to the feedback capacitor.

8. A low drop out voltage regulator comprising:

a transistor for generating an output of the low drop out voltage regulator; and

an integrator coupled to the transistor, the integrator comprising:

a differential amplifier for controlling the operations of the transistor; and

a feedback capacitor connected between the output and an input of the differential amplifier, wherein a voltage at the output is dependent on a charge across the feedback capacitor.

9. A low drop out voltage regulator according to claim 8 , further comprising a switched capacitor divider network having its input connected to the output and its output connected to feedback capacitor.

10. A low drop out voltage regulator according to claim 9 , wherein the switched capacitor divider network is periodically operational to apply charge to the feedback capacitor.

11. A low drop out voltage regulator according to claim 10 , wherein the switched capacitor divider network includes first and second capacitors connected in parallel and a plurality of controllable switches.

12. A low drop out voltage regulator according to claim 11 , wherein during a first phase of operation the plurality of switches are configured to couple the first capacitor between the output and ground, and to couple both terminals of the second capacitor to ground.

13. A low drop out voltage regulator according to claim 12 , wherein during a second phase of operation the plurality of switches are configured to couple the first capacitor in parallel with the second capacitor.

14. A low drop out voltage regulator according to claim 13 , wherein during a third phase of operation the plurality of switches are configured to couple the first and second capacitors to the feedback capacitor.

15. A method comprising:

amplifying a difference between a voltage from a stored charge across a feedback capacitor and a reference voltage to generate a control signal;

controlling a conductance of a transistor with the control signal to generate an output voltage; and

based on the output voltage, adjusting the stored charge on the feedback capacitor so that the output voltage is dependent on the charge across the feedback capacitor.

16. The method according to claim 15 , further comprising periodically applying a charge to the feedback capacitor via a switched capacitor divider network.

17. The method according to claim 16 , wherein the switched capacitor divider network includes first and second capacitors connected in parallel and a plurality of controllable switches.

18. The method according to claim 17 , wherein during a first phase of operation coupling the first capacitor between the output and ground, and coupling both terminals of the second capacitor to ground.

19. The method according to claim 18 , wherein during a second phase of operation coupling the first capacitor in parallel with the second capacitor.

20. The method according to claim 19 , wherein during a third phase of operation coupling the first and second capacitors to the feedback capacitor.