IP Library Granted Patent US 9,013,391
Granted Patent B2
US 9,013,391 · App. 13/789,297 · Granted Apr 21, 2015

Output control circuit, scanning line driving circuit of electro-optic device, electro-optic device and electronic apparatus

Inventor: Shinsuke Fujikawa (Chino, JP)
Assignee: Seiko Epson Corporation
G09G5/003H03K3/015G09G2310/0286G09G3/2022G09G3/3677G09G2310/0216G09G2310/08
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Quick Facts
Patent No.
US 9,013,391
App. No.
13/789,297
Granted
Apr 21, 2015
Kind
B2
Abstract

An output control circuit is configured to have a first circuit which includes a NOT circuit, a NAND circuit and a transmission gate as a first sub circuit, and a second circuit which includes a NAND circuit as a second sub circuit. The NAND circuit controls a transmission to the NAND circuit of the enable signal by the transmission gate based on signal which has been logic reversed by the NOT circuit and the NAND circuit.

Claims (40)

1. An output control circuit comprising:

a first circuit which includes a plurality of first sub circuits; and

a second circuit which includes a plurality of second sub circuits,

wherein one first sub circuit among the plurality of first sub circuits inputs one input signal and enable signal,

wherein one second sub circuit among the plurality of second sub circuits inputs the enable signal when the enable signal is transmitted from the one first sub circuit,

wherein the one second sub circuit outputs a first output signal,

wherein the one first sub circuit inputs the first output signal,

wherein another second sub circuit different from the one second sub circuit among the plurality of second sub circuits inputs the first output signal, and

wherein the one second sub circuit inhibits the one output signal from becoming an active level when the output signal of the other second sub circuit is at an active level.

2. The output control circuit according to claim 1 , wherein the one first sub circuit includes:

a logical circuit which inputs the one input signal and the one output signal; and

a switch which takes either of two states of on or off state in response to an output signal of the logical circuit in the middle of the course where the enable signal is supplied to the second sub circuit.

3. The output control circuit according to claim 1 ,

wherein the one first sub circuit includes a logical circuit that outputs a second output signal based on one of the first output signal and the another input signal.

4. The output control circuit according to claim 3 ,

wherein an input signal input to the logical circuit is a signal transmitted from a shift register.

5. A scanning line driving circuit which drives each of scanning lines, comprising:

a shift register which causes a pulse signal which becomes an active level in a mutually exclusive manner to be sequentially output corresponding to each of the scanning lines; and

an output control circuit according to claim 1 which is provided for each of a predetermined number of the scanning lines,

wherein the output control circuit inputs an enable signal and a pulse signal corresponding to the predetermined number of the scanning lines so as to be transmitted to the corresponding scanning line.

6. An electro-optic device comprising:

a pixel corresponding to an intersection of a scanning line and a data line; and

the scanning line driving circuit according to claim 5 which drives the scanning line.

7. An electronic apparatus comprising:

the electro-optic device according to claim 6 .

8. An output control circuit comprising:

a first circuit including a plurality of first sub circuits in which at least one first sub circuit among the plurality of first sub circuits inputs a first input signal and an enable signal and at least another first sub circuit among the plurality of first sub circuits inputs another input signal and the enable signal; and

a second circuit including a plurality of second sub circuits in which one second sub circuit among the plurality of second sub circuits inputs the enable signal when the enable signal is transmitted from one of the two first sub circuits,

wherein a second sub circuit other than the one second sub circuit among the plurality of second sub circuits inputs an output signal from the one second sub circuit.

9. The output control circuit according to claim 8 ,

wherein one of the two first sub circuits inputs one of a first output signal output from the one second sub circuit and the another input signal.

10. A scanning line driving circuit which drives each of scanning lines, comprising:

a shift register which causes a pulse signal which becomes an active level in a mutually exclusive manner to be sequentially output corresponding to each of the scanning lines; and

an output control circuit according to claim 8 which is provided for each of a predetermined number of the scanning lines,

wherein the output control circuit inputs an enable signal and a pulse signal corresponding to the predetermined number of the scanning lines so as to be transmitted to the corresponding scanning line.

11. An electro-optic device comprising:

a pixel corresponding to an intersection of a scanning line and a data line; and

the scanning line driving circuit according to claim 10 which drives the scanning line.

12. An electronic apparatus comprising:

the electro-optic device according to claim 11 .

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 17, 2024
From: SEIKO EPSON CORPORATION
To: 138 EAST LCD ADVANCEMENTS LIMITED
Reel/Frame 067131/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 7, 2013
From: FUJIKAWA, SHINSUKE
To: SEIKO EPSON CORPORATION
Reel/Frame 029946/0440 →
Priority Claims (1)
JP 2012-055389 · Mar 13, 2012 · national
Continuity (1)
Related Publication 20130241812A1 · Sep 19, 2013